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®
Data Sheet
February 8, 2005
ISL6425
www.DataSheet4U.com
FN9176.1
Single Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-top Box Designs
The ISL6425 is a highly integrated solution for supplying
power and control signals from advanced satellite set-top
box (STB) modules to the low noise block (LNB). This device
is comprised of a current-mode boost PWM and a low-noise
linear regulator, along with the circuitry required for I2C
device interfacing and for providing DiSEqC standard control
signals to the LNB.
A regulated output voltage is available at the output terminal
(VOUT) to support the operation of the antenna port in
advanced satellite STB applications. The regulated output
may be set to either 13V or 18V by use of the voltage select
command (VSEL) through the I2C bus. Additionally, to
compensate for the voltage drop in the coaxial cable, the
voltage may be increased by 1V with the line length
compensation (LLC) feature. An enable command sent on
the I2C bus provides standby mode control for the PWM and
linear combination, disabling the output to conserve power.
A current-mode boost converter provides the linear regulator
with an input voltage that is set to the required output
voltage, plus 1.2V (typ.) to insure minimum power
dissipation. This maintains a constant voltage drop across
the linear pass element, while permitting an adequate
voltage range for tone injection.
The device is capable of providing 750mA (typ.).
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
ISL6425ER
-20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6425ER-T
32 Ld 5x5 QFN Tape and Reel L32.5x5
ISL6425ERZ
(Note)
-20 to 85
32 Ld 5x5 QFN L32.5x5
(Pb-free)
ISL6425ERZ-T
(Note)
32 Ld 5x5 QFN Tape and Reel
(Pb-free)
L32.5x5
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWM with >92% Efficiency
- Selectable 13V or 18V Outputs
- Digital Cable Length Compensation (1V)
• External Pin to Select 13V/18V Options
• DSQIN and SEL18V pins are 2.5V logic compatible
• I2C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Fully Functional 3.3V, 5V Operation up to 400kHz
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
• Internal Over-Temperature Protection and Diagnostics
• Internal Overload and Overtemp Flags (Visible on I2C)
• LNB Short-Circuit Protection and Diagnostics
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint
• Pb-free available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
References
• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinout
ISL6425
ISL6425 (32 LEAD 5x5 QFN)
TOP VIEW
www.DataSheet4U.com
32 31 30 29 28 27 26 25
PGND 1
24 CPSWOUT
NC 2
23 NC
SGND 3
22 NC
SEL18V 4
21 NC
NC 5
20 AGND
BYPASS 6
19 VOUT
PGND 7
18 DSQIN
GATE 8
17 TCAP
9 10 11 12 13 14 15 16
2 FN9176.1
February 8, 2005

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Typical Application Schematic
VIN
C16
1uF
0
C17
47nF
0
C18 1n
C6
2 56uF
L2
33uH
0
1 Q2
FDS6612A
5
6
7
8
D2
STPS2L40U
C4
56uF
0
0
0
0
C8 1uF
1
2
3
4
5
6
7
8
PGND
NC
SGND
SEL18V
NC
BYP
PGND
GATE
U1
ISL6425ER
CPSWOUT
NC
NC
NC
AGND
VOUT
DSQIN
TCAP
24
23
22
21
20
19
18
17
0
R6
18
4
3
2 R5 100
1
R2
0.1 C2
100pF
0
C13
10uF
0
0
L3 4.7uH
12
C9 1.5n R8 68K
C10 33p
C14 C15
10uF 10uF
00
C20
0.22uF
0
R10 1k
R11 1k
0
D5 STPS2L40U
D3
STPS2L40U
0
C22
0.1uF
0
VLNB1
R13
100k
0
DSQIN1
SCL
SDA
SEL18V1

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Block Diagram
COUNTER
10 GATE
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
OLF
DCL
PWM
LOGIC
Q
S
CLK
OC
7
SEL18V
E PAD
PGND
CS
11
CS ILIM
AMP
SLOPE
COMPENSATION
13 COMP
12 FB
VREF
BAND GAP
REF VOLTAGE
REF
VOLTAGE
ADJ
14 VSW
ISEL
EN
ENT
OLF
I2C
INTERFACE
SDA
ADDR
SCL
OTF
LLC VSEL
DCL
CLK OSC.
220kHz
BGV
÷ 10 AND
WAVE SHAPING
TONE
INJ
CKT
22kHz
TONE
20 VOUT
28 VCC
ON CHIP
LINEAR
UVLO
6
SGND
POR
SOFT-START
INT 5V
SOFT-START
EN
+-
OTF
THERMAL
SHUTDOWN
CHARGE PUMP
CPSWOUT
9 21 18 25
SDA
ADDR
SCL
15
16
17
ENT
DSQIN
19
CPVOUT
CPSWIN
27
26

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ISL6425
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN, SEL18V) . . . . . . . . . . . . . . -0.5V to 7V
Output Current . . . . . . . . . . . . . . . . . . . . Externally/Internally Limited
Thermal Information
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Thermal Resistance
θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . .
32
4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
NOTE: The device junction temperature should be kept below
150°C. Thermal shut-down circuitry turns off the device if junction
temperature exceeds +150°C typically.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temperature” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VCC
ENT
=
=
12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN = H, LLC =
L, DCL = L, DSQIN = L, IOUT = 12mA, unless otherwise noted. See software description section for
L,
I2C
access to the system.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range
8 12 14
V
Standby Supply Current
EN = L
- 1.5 3.0 mA
Supply Current
UNDERVOLTAGE LOCKOUT
IIN EN = LLC = VSEL = ENT = H, No Load
-
4.0 8.0
mA
Start Threshold
7.5 - 7.95 V
Stop Threshold
7.0 - 7.55 V
Start to Stop Hysteresis
350 400 500
mV
SOFT-START
COMP Rise Time (Note 2)
(Note 4)
- 1024 - Cycles
OUTPUT VOLTAGE
Output Voltage (Note 3)
Line Regulation
Load Regulation
Dynamic Output Current Limiting
VOUT
VOUT
VOUT
VOOU
DVOUT
DVOUT
IMAX
VSEL = L, LLC = L
VSEL = L, LLC = H
VSEL = H, LLC = L
VSEL = H, LLC = H
VIN = 8V to 14V; VOUT = 13V
VIN = 8V to 14V; VOUT = 18V
IO = 12mA to 450mA
DCL = L, ISEL = L
DCL = L, ISEL = H
12.74 13.0 13.26
13.72 14.0 14.28
17.64 18.0 18.36
18.62 19.0 19.38
- 4.0 40.0
- 4.0 60.0
- 50 80
425 - 550
775 - 950
V
V
V
V
mV
mV
mV
mA
mA
Dynamic Overload Protection Off Time
TOFF DCL = L, Output Shorted (Note 4)
- 900 -
ms
Dynamic Overload Protection On Time
TON
- 20 -
ms
22kHz TONE
Tone Frequency
Tone Amplitude
Tone Duty Cycle
Tone Rise or Fall Time
ftone
Vtone
dctone
Tr, Tf
ENT = H
ENT = H
ENT = H (Note 5)
ENT = H
20.0 22.0 24.0
550 680 900
40 50 60
5 8 14
kHz
mV
%
µs
5 FN9176.1
February 8, 2005