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®
Data Sheet
September 13, 2005
ISL6424
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FN9175.3
Dual Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6424 is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is comprised of two independent current-
mode boost PWMs and two low-noise linear regulators along
with the circuitry required for 22kHz tone generation,
modulation and I2C device interface. The device makes the
total LNB supply design simple, efficient and compact with
low external component count.
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 1.2V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM are
set to 13V or 18V by independent voltage select commands
(VSEL1, VSEL2) through the I2C bus. Additionally, to
compensate for the voltage drop in the coaxial cable, the
selected voltage may be increased by 1V with the line length
compensation (LLC) feature. All the functions on this IC are
controlled via the I2C bus by writing 8 bits on System
Register (SR, 8 bits). The same register can be read back,
and two bits will report the diagnostic status. Separate enable
commands sent on the I2C bus provide independent standby
mode control for each PWM and linear combination, disabling
the output into shutdown mode.
Each output channel is capable of providing 750mA of
continuous current. The overcurrent limit can be digitally
programmed. The SEL18V pin allows the 13V to 18V
transition with an external pin, overriding the I2C input.
The ISL6424 is offered in a 32 Ld 5x5 QFN.
Features
• Single Chip Power Solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC-DC Converter and I2C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with > 92% Efficiency
- Selectable 13V or 18V Outputs
- Digital Cable Length Compensation (1V)
• I2C Compatible Interface for Remote Device Control
- Registered Slave Address 0001 00XX
- Full 3.3V/5V Operation up to 400kHz
• External Pins to Select 13V/18V Option
• DSQIN1&2 and SEL18V1&2 pins 2.5V Logic Compatible
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
• Internal Over-Temperature Protection and Diagnostics
• Internal Overload and Overtemp Flags (Visible on I2C)
• LNB Short-Circuit Protection and Diagnostics
• QFN Package
- Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Product Outline
- Near Chip-Scale Package Footprint
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
References
• Tech Brief 389 (TB389) - “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”; Available
on the Intersil website, www.intersil.com
Ordering Information
PART # *
PART
TEMP.
PKG.
MARKING (°C) PACKAGE DWG. #
ISL6424ER
ISL6424ER -20 to 85 32 Ld 5x5 QFN L32.5x5
ISL6424ERZ (Note) ISL6424ERZ -20 to 85 32 Ld 5x5 QFN L32.5x5
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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Pinout
ISL6424 (QFN)
TOP VIEW
ISL6424
32 31 30 29 28 27 26 25
PGND2 1
24 CPSWOUT
CS2 2
23 TCAP2
SGND 3
22 DSQIN2
SEL18V1 4
SEL18V2 5
ISL6424ER
21 VO2
20 AGND
BYP 6
19 VO1
PGND1 7
18 DSQIN1
GATE1 8
17 TCAP1
9 10 11 12 13 14 15 16
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2 FN9175.3
September 13, 2005

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Block Diagram
4
14 15 16
COUNTER
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
OLF1
DCL
SEL18V1
OLF2
DCL
OVERCURRENT
PROTECTION
LOGIC SCHEME 2
COUNTER
8 GATE1
PGND1
7
PWM
LOGIC
Q
S
CLK1
OC1
9 CS1
CS ILIM1
AMP
11 COMP1
SLOPE
COMPENSATION
10 FB1
VREF1
12 VSW1
19 VO1
BAND GAP
REF VOLTAGE
REF
VOLTAGE
ADJ1
SDA
ADDR SCL
OC2
CLK2
PWM
LOGIC
Q
S
GATE2
PGND2
ISEL1
EN1
ENT1
OTF
LLC1
OLF1 OLF2
I2C
INTERFACE
VSEL1
VSEL2
ISEL2
EN2
ENT2
DCL
LLC2
ILIM2 CS
AMP
SLOPE
COMPENSATION
CS2
BGV
CLK1
OSC.
220kHz
CLK2
÷ 10 &
WAVE SHAPING
TONE
INJ
CKT 1
22kHz
TONE
TONE
INJ
CKT 2
BGV
REF
VOLTAGE
ADJ2
VREF2
COMP2
FB2
SEL18V2
VSW2
VO2
+-
ENT2
+-
32
1
2
30
31
5
29
21
27 VCC
ON CHIP
LINEAR
UVLO
3
SGND
POR
SOFT-START
INT 5V
SOFT-START
EN1/EN2
6
ENT1
CPVOUT
26
OTF
THERMAL
SHUTDOWN
CHARGE PUMP CPSWIN
CPSWOUT
25
20 17 18 22 23
24

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Typical Application Schematic
P1
VIN
P2
GND
E
L3
C25
1µF
100nH
C4
1µF
C27A
10µF
C27B
10µF
E
E
VOUT1 P3
D3
STPS2L40U
GND P4
+5V/+3.3V P7
C21
0.1µF
E
C1B
10µF
+ C1A
56µF
C15A +
56µF
L1 C9 C10
33µH
R1 C3
5.1 1500pF
D1
8 Q1 1
72
63
54
+
C5
STPS2L40U
FDS6612A
R2
E
0.047µF
C2
E 1µF
C8
1µF
D
1000pF
C21
4.7µF C12 E
1µF D
56µF
C5
33pF
C24 0.10
E 100pF
R9
100
R3 C7
68K 1500pF
C30
0.01µF
8
9
7
11
10
12
19
18
GATE1
CS1
PGND
COMP1
FB1
VSW1
VO1
DSQIN1
33 EP
U1
ISL6424
GATE2
CS2
PGND2
COMP2
FB2
VSW2
VO2
DSQIN2
32
2
1
30
31
29
21
22
SEL18V2
EE
SP1 D
C15
10µF
L2
E 33µH
C15 R6
1 Q2 8
27
36
45
FDS6612A
D2
STPS2L40U + C17
R4 56µF
R10 C24 0.10
100
100pF
E
C13
1500pF
R5
68K
C14
33pF
5.1
C28A
10µF
E
C28B
10µF
C31
0.01µF
E
SP2
E
C19
0.1µF
E
OUT VL
IN VL
R13 R14 R16 R17 R15
100K 100K 100K 100K 100K
L4
100nH
C18
1µF
C26
1µF
E
P5 VOUT2
D4
STPS2L40U
P6 GND
E
C29
0.1µF
J1
SCL
GND
GND
SDA
1
2
3
4
1
2
3
4
1x4
D
R12 R11
10K 10K
R7
100
R8
100
SW1
1 12 DISQ1
2 11 DISQ2
3 10 SEL18V1
4 9 SEL18V2
5 8 ADDR
67
DDIP_SW5_SPST
P9 SEL18V1
P8 SEL18V2

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ISL6424
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN 1&2, SEL18V 1&2) . . . . . . -0.5V to 7V
Thermal Information
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Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
32
4
Maximum Junction Temperature (Note 3) . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -40°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Operating Temperature Range . . . . . . . . . . . . . . . . . . -20°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. The device junction temperature should be kept below 150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
+150°C typically.
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. EN1 = EN2 = H,
LLC1 = LLC2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, Iout = 12mA, unless otherwise noted.
See software description section for I2C access to the system.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Operating Supply Voltage Range
8 12 14
V
Standby Supply Current
EN1 = EN2 = L
- 1.5 3.0 mA
Supply Current
IIN EN1 = EN2 = LLC1 = LLC2 = VSEL1 =
VSEL2 = ENT1 = ENT2 = H, No Load
-
4.0 8.0
mA
UNDERVOLTAGE LOCKOUT
Start Threshold
7.5 - 7.95 V
Stop Threshold
7.0 - 7.55 V
Start to Stop Hysteresis
350 400 500
mV
SOFT-START
COMP Rise Time (Note 4)
(Note 5)
- 512 - Cycles
Output Voltage (Note 5)
Line Regulation
Load Regulation
Dynamic Output Current Limiting
VO1
VO1
VO1
VO1
VO2
VO2
VO2
VO2
DVO1,
DVO2
DVO1,
DVO2
IMAX
VSEL1 = L, LLC1 = L
VSEL1 = L, LLC1 = H
VSEL1 = H, LLC1 = L
VSEL1 = H, LLC1 = H
VSEL2 = L, LLC2 = L
VSEL2 = L, LLC2 = H
VSEL2 = H, LLC2 = L
VSEL2 = H, LLC2 = H
VIN = 8V to 14V; VO1, VO2 = 13V
VIN = 8V to 14V; VO1, VO2 = 18V
IO = 12mA to 350mA
IO = 12mA to 750mA (Note 6)
DCL = L, ISEL1/2 = L
DCL = L, ISEL1/2 = H (Note 6)
12.74 13.0 13.26
13.72 14.0 14.28
17.64 18.0 18.36
18.62 19.0 19.38
12.74 13.0 13.26
13.72 14.0 14.28
17.64 18.0 18.36
18.62 19.0 19.38
- 4.0 40.0
- 4.0 60.0
- 50 80
- 100 200
425 - 550
775 850 950
V
V
V
V
V
V
V
V
mV
mV
mV
mV
mA
mA
Dynamic Overload Protection Off Time
TOFF DCL = L, Output Shorted (Note 6)
- 900 -
ms
Dynamic Overload Protection On Time
TON
- 20 -
ms
5 FN9175.3
September 13, 2005