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[ASAHI KASEI]
[AK7740ET]
AK7740ET
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
1. General Description
The AK7740 is a highly integrated audio processing IC, including four 24-bit output D/A channels, a stereo 24-bit
input A/D, and an audio DSP. High quality analog output performance is provided by the quad DAC with 97dB
dynamic range, and the stereo ADC with 98dB dynamic range. The converters support sampling frequencies from
32kHz to 48kHz. This device includes 72kbits of SRAM audio delay that is suitable for simulated sound fields. The
DSP is optimized for audio signal processing. The design allows up to 512 execution lines per audio sample cycle,
with multiple functions per line. The AK7740 is ideal for sound field control applications, including echo, 3D,
parametric equalization, and speaker compensation. It is housed in a 48-lead LQFP package.
2. Features
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- Word length:
24-bit (Data RAM)
- Instruction cycle time: 40ns (512fs, fs=48kHz )
- Multiplier: 24 x 16 40-bit
- Divider: 24 / 24 16-bit or 24-bit
- ALU:
34-bit arithmetic operation (overflow margin: 4-bits)
- 24-bit arithmetic and logic operation
- Shift+Register: 1, 2, 3, 4, 6, 8 and 15 bits shifted left
- 1, 2, 3, 4, 8 , 14 and 15 bits shifted right
- Other numbers in parentheses are restricted. Provided with indirect shift function
- Program RAM:
- Coefficient RAM:
512 x 32-bit
512 x 16-bit
- Data RAM:
- Offset RAM:
256 x 24-bit
48 x 13-bit
- (6144 x 12-bit / 3072 x 24-bit / 4096 x 12-bit + 1024 x 24-bit )
- Internal Memory: 72kbit SRAM
- Sampling frequency: 32kHz to 48kHz
- Serial interface port for micro-controller
- Master clock: 512fs
- Master/Slave operation
- Serial signal input port ( 2 to 4 ch ): 16/20/24-bit : Output port ( 2 ch ): 24-bit
ADC: 2 channels
- 24-bit 64x over-sampling delta sigma
- DR, S/N : 98dBA ( full-differential Input )
- S/(N+D) : 89dB
- Digital HPF (fc = 1Hz)
- Single-ended or full-differential Input
DAC: 4 channels
- 24-bit 128x over-sampling advanced multi-bit
- DR, S/N : 97dBA
- S/(N+D) : 89dB
- Single ended or differential output
Input Selector
- 1 full-differential and 4 single-ended Input
Other
- Power supply: +3.3V±10%
- Operating temperature range: -10°C~70°C
- Package: 48pin LQFP (0.5mm pitch)
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[ASAHI KASEI]
[AK7740ET]
3. Block diagram
LRCLK BITCLK CLKOUT XTI XTO SMODE
SDOUTA
OUTAE
LRCLK BITCLK CLKOUT XTI XTO SMODE INIT_RESET
CONTROLLER
S_RESET
SDINA
SDIN
RQ
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SO
SCLK
RDY
DRDY
JX
RQ
SI
SO
SCLK
RDY
DRDY
JX
SW3
DSP
SDINA
SDIN
ISEL[2:0]
SDOUTD1
SDOUTD2
SDOUT
ADC AINL-
AINL+
SW0
SDATA
AINR-
AINR+
SW2 VREF
SDATA DAC1 AOUTL
AOUTR
SW2
SDATA DAC2
AOUTL
AOUTR
SW1
72kbit DLRAM
* SW1,SW2,SW3,ISEL[2:0],
OUTAE control register
Note) A
B
C
Q When C is “L”(0) then A connects with Q.
INIT_RESET
S_RESET
AINL-
AINL+
AINL1
AINL2
AINL3
AINL4
AINR-
AINR+
AINR1
AINR2
AINR3
AINR4
VREFH
VCOM
AOUTL1
AOUTR1
AOUTL2
AOUTR2
SDOUT
This block diagram is a simplified illustration of the AK7740; it is not a circuit diagram.
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[ASAHI KASEI]
‹ AK7740 DSP Block diagram
CP0,CP1
CRAM
512 X 16
DP0,DP1
DRAM
256 X 24
CBUS(16bit)
DBUS(24bit)
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MPX16
MPX24
XY
Multiply
16 X 24 -> 40
40bit
24bit
34bit
MUL DBUS
SHIFT
34bit
AB
ALU1
34bit
Overflow Margin: 4bit
DR0 3
24bit
Over Flow Data
Generator
[AK7740ET]
DLP0,DLP1
DLRAM
6K X 12 or 3K X 24
4K X 12 & 1K X 24
OFRAM
48 X 13
CMP(Compress & Expand)
Micom I/F
Control
Serial I/F
PRAM
512 X 32
PC
Stack : 1level
TMP 8 X 24bit
PTMP 24bit X 6(LIFO)
2 X 24 bit
ADC
2 X 24/20/16bit
Divider
24 ÷ 24 24
SDIN
2 X 24bit
2 X 24bit
DAC1
DAC2
2 X 24bit
SDOUT
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(1) Pin layout
4. Description of Input/Output Pins
[AK7740ET]
AINL3
AINR2
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AINL2
AINR1
AINL1
VREFH
AVDD
AVSS
DVSS
DVDD
XTI
XTO
1
2
3
4
5
6
7
8
9
10
11
12
48pin LQFP
(TOP VIEW)
36 AOUTL2
35 AOUTR2
34 BVSS
33 DVSS
32 DVDD
31 INIT_RESET
30 S_RESET
29 RQ
28 SCLK
27 SI
26 SO
25 RDY
Note) JX,SDIN and SDINA are Pull-down pins
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[AK7740ET]
(2) Pin function
Pin No.
1
2
3
4
5
6
Pin name
AINL3
AINR2
AINL2
AINR1
AINL1
VREFH
7 AVDD
8 AVSS
9 DVSS
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11 XTI
12 XTO
13 CLKO
14 JX
15 SMODE
16 LRCLK
17 BITCLK
18 SDIN
19 SDINA
I/O Function
I ADC single-ended analog Lch input pin 3
I ADC single-ended analog Rch input pin 2
I ADC single-ended analog Lch input pin 2
I ADC single-ended analog Rch input pin 1
I ADC single-ended analog Lch input pin 1
I Analog reference voltage input
Connect to AVDD (pin 7), and bypass with 0.1uF and
10uF capacitors between this pin and AVSS.
- Analog power supply 3.3V typical
- Analog ground
- Digital ground
- Digital power supply 3.3V typical
Master clock input
I Connect a crystal oscillator between this pin and the XTO pin,
or input an external CMOS clock signal to the XTI pin.
Crystal oscillator output
O When a crystal oscillator is used, connect between XTI and XTO.
When an external clock is used, keep this pin open
Clock output
O Outputs the XTI clock.
Allows the output to be set to "L" by control register setting.
I External condition jump (pulldown)
Slave/master mode selector
I Sets LRCLK and BITCLK to input or output mode.
SMODE="L": Slave mode (clock input mode)
SMODE="H": Master mode (clock output mode)
LR channel select clock
I/O SMODE="L": Slave mode: Inputs the fs clock
SMODE="H": Master mode: Outputs the fs clock
Serial bit clock
I/O SMODE="L": Slave mode: Inputs 64 fs or 48 fs clocks
SMODE="H": Master mode: Outputs 64 fs clocks
DSP serial data input ( Pulldown)
I Compatible with MSB/LSB justified 24, 20 and 16 bits.
DSP serial data input (Pulldown)
I When using the ADC, leave open or connect to DVSS.
Compatible with MSB justified 24 bits.
Classification
Analog section
Analog
Power Supply
Digital
Power Supply
System clock
System clock
Condition input
Control
System clock
Digital section
Serial input data
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