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INIC-1608
INIC-1608
USB to SATA Bridge
Specification
Version 1.0
August 10, 2007
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Change History:
Create on 07/06/2007.
INIC-1608
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INIC-1608
Table of Contents
1. Introduction:............................................................................................................................................................ 6
1.1 Feature Summary.................................................................................................................... 6
1.2 Firmware/Software Support .................................................................................................. 7
1.3 Devices Support..................................................................................................................... 7
2. INIC-1608 Block Diagram:..................................................................................................................................... 8
3. Pin-Out Diagram: .................................................................................................................................................... 9
4. Pin Signal Description: (48-pin package).............................................................................................................. 10
4.1 USB Interface ...................................................................................................................... 10
4.2 SATA Interface (Analog pins) ............................................................................................ 10
4.3 System Interface .................................................................................................................. 10
4.4 Miscellaneous Interface....................................................................................................... 10
4.5 NVRAM Interface ............................................................................................................... 11
4.6 GPIO Interface..................................................................................................................... 11
4.7 Power Regulator pins.......................................................................................................... 11
4.8 Power/GND ......................................................................................................................... 11
5. Register Address Mapping: ................................................................................................................................... 12
5.1 General Registers................................................................................................................. 12
5.2 Buffers ................................................................................................................................. 12
5.3 USB Control Registers ........................................................................................................ 13
5.4 SATA Control Registers...................................................................................................... 13
5.5 Data BUFFER...................................................................................................................... 13
5.6 USB Registers...................................................................................................................... 13
5.7 Data Space Mapping............................................................................................................ 14
5.8 Code Space: Internal ROM: ................................................................................................ 14
6. Programming Guide: ............................................................................................................................................. 15
6.1 CPU Write NVRAM.................................................................................................................................................. 15
6.2 CPU Read NVRAM................................................................................................................................................... 15
6.3 CPU Poll NVRAM..................................................................................................................................................... 15
6.4 Host Read/Write 8051 data space from USB .......................................................................... 15
6.5 NVRAM Download from USB cable........................................................................................ 16
7. Register Descriptions: ........................................................................................................................................... 17
7.1 BUFFER Reset Register (0x40A3) ..................................................................................... 17
7.2 Test Control Register (0x40A6) .......................................................................................... 17
7.2.0 Test Control Register (0x40A7) .......................................................................................... 17
7.2.1 LED_spd register (0x40AC).............................................................................................. 17
7.2.2 MiscEn register (0x40AD) ................................................................................................ 18
7.3 MiscCtl register (0x40AF): This 8-registers is in lclk domain (37.5 MHz)......................... 18
7.4 SoftRst register (0x40B0).................................................................................................... 18
7.5 DMA Flush register (0x40B1)............................................................................................. 18
7.6 USB Channel Set/Clear register (0x40B2 Set) (0x40B3 Clear).......................................... 18
7.7 Dir/D2BEn register (0x40B4) ............................................................................................. 19
7.8 Run register (0x40B5) ......................................................................................................... 19
7.9 SATA Config register (0x40B6) ........................................................................................... 19
7.10 SATA Reset register (0x40B7)............................................................................................ 20
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7.11 I2C_Addr Register (0x40E0)............................................................................................. 20
7.12 I2C_Data Register (0x00xE1) (I2C Data port).................................................................. 20
7.13 I2C_Ctrl Register (0x40E2) (I2C Control Code) .............................................................. 20
7.14 I2C_COMM Register (0x40E3) ........................................................................................ 20
7.15 I2C_Status Register (0x40E4) ........................................................................................... 21
7.16 OTB_Counter Register (0x40E8)...................................................................................... 21
7.16.1 OTB_Ctrl Register (0x40E9)...................................................................................... 21
7.16.2 OTB_INT_Enable Register (0x40EA) ....................................................................... 21
7.17 usb_INT_Enable Register (0x40F0).................................................................................. 21
7.18 SATA_INT_Enable Register (0x40F2)............................................................................. 22
7.19 SATA_BUSY_INT Register (0x40F3) ............................................................................. 22
7.20 GPIO_P_INT_Enable Register (0x40F4).......................................................................... 23
7.21 GPIO_N_INT_Enable Register (0x40F5) ......................................................................... 23
7.22 Buffer Clear Register (0x40F7)......................................................................................... 23
7.23 GPIO_Enable Register (0x40F8)....................................................................................... 23
7.24 GPIO_Data Register (0x40F9) .......................................................................................... 23
7.25 GPIO_Output_Enable Register (0x40FA)......................................................................... 23
7.26 USB Clear Register (0x40FB)........................................................................................... 24
7.27 Buffer Address Map ............................................................................................................ 24
7.28 USB Control ........................................................................................................................ 24
8. SATA CHANNEL REGISTERS (0x4800-0x483F): ............................................................................................ 24
8.1 Command Parameter Blocks (CPB) Structure Definition................................................... 24
8.1.1. ATA Error Shadow.............................................................................................................. 24
8.1.2. ATA Status Shadow ............................................................................................................ 25
8.1.3. Control Flags ....................................................................................................................... 25
8.1.4. Reserved .............................................................................................................................. 25
8.1.5. ATA Feature Shadow .......................................................................................................... 25
8.1.6. ATA Extended Feature Shadow .......................................................................................... 25
8.1.7. ATA Device/Head Shadow ................................................................................................. 25
8.1.8. ATA Sector Count Shadow ................................................................................................. 25
8.1.9. ATA Extended Sector Count Shadow ................................................................................. 26
8.1.10. ATA Sector Number Shadow............................................................................................ 26
8.1.11. ATA Extended Sector Number Shadow............................................................................ 26
8.1.12. ATA Cylinder Low Shadow.............................................................................................. 26
8.1.13. ATA Extended Cylinder Low Shadow.............................................................................. 26
8.1.14. ATA Cylinder High Shadow ............................................................................................. 26
8.1.15. ATA Extended Cylinder High Shadow ............................................................................. 26
8.1.16. ATA Command Shadow ................................................................................................... 26
8.1.17. ATA Control Shadow........................................................................................................ 27
8.2 SATA PHY Low Control Register (4820h) ........................................................................ 27
8.3 SATA PHY HighControl Register (4821h)......................................................................... 27
8.4 SATA PHY Low Status Register (4822h)........................................................................... 27
8.5 SATA PHY High Status Register (4823h) .......................................................................... 27
8.6 SATA Status Register (4830h-4833h)................................................................................. 27
8.7 SATA Error Register (4834h-4837h) .................................................................................. 28
8.8 SATA Control Register (4838h-483Bh).............................................................................. 28
8.9 Bist Mode Register (483Ch)................................................................................................ 28
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8.10 Sata_busy_drq_status(483Dh)............................................................................................. 28
8.11 Bist_Act_Fis_0 Register (483Eh)........................................................................................ 28
8.12 Bist_Act_Fis_1 Register (483Fh)........................................................................................ 28
8.13 Bist_Act_Fis_2 Register (4840h) ........................................................................................ 28
8.14 Bist_Act_Fis_3 Register (4841h) ........................................................................................ 28
8.15 Bist_Act_Fis_4 Register (4842h) ........................................................................................ 28
8.15 Bist_Act_Fis_5 Register (4843h) ........................................................................................ 29
8.16 Bist_Act_Fis_6 Register (4844h) ........................................................................................ 29
8.17 Bist_Act_Fis_7 Register (4845h) ........................................................................................ 29
8.18 Bist_Act_Fis_8 Register (4846h) ........................................................................................ 29
9. Data BUFFER: ...................................................................................................................................................... 29
10. USB Registers: ...................................................................................................................................................... 29
10.1 Device Status (Dev_Status[7:0], 0x6020) ............................................................................. 29
10.2 Function Address (Funct_Adr[7:0], 0x6021) ........................................................................ 29
10.3 Test Mode (Test_mode[7:0], 0x6022)................................................................................... 30
10.4 End Point TX Data Length Low Bytes (Ep_TxLength[7:0], 0x6025) .................................. 30
10.5 End Point TX Data Length High Bytes (Ep_TxLength[15:8], 0x6026) ............................... 30
10.6 End Point 0 Status/Control (EP0_Status [7:0], 0x6030: Set, 0x6031: Clear) ....................... 30
10.7 End Point 0 Status/Control2 (EP0_Status2 [7:0], 0x6032: Set, 0x6033: Clear, Bulk-IN) .... 30
10.8 End Point TX Data Length Low Bytes (Ep0TxLength [7:0], 0x6034) ................................. 31
10.9 Setup Packet (Hdr0—Hdr7 [7:0], 0x6038—0x603F) ........................................................... 31
10.10 End Point 1 Status/Control (EP1_Status [7:0], 0x6040: Set, 0x6041: Clear, Bulk-IN) ...... 31
10.11 End Point 2 Status/Control (EP2_Status [7:0], 0x6050: Set, 0x6051 Clear, Bulk-OUT) ... 31
10.12 Usb_rxLength (usb_rxLength[7:0], 0x6052, Bulk-OUT) ................................................... 32
10.13 End Point 3 Status/Control (EP3_Status [7:0], 0x6060: Set, 0x6061: Clear, INTR-IN) .... 32
10.14 End Point TX Data Length Low Bytes (Ep3TxLength [7:0], 0x6062) ............................... 32
10.15 Total Count0 (TotalCnt[7:0], 0x6070 TotalCnt0) ............................................................... 32
10.16 Total Count1 (TotalCnt[15:8], 0x6071 TotalCnt1) ............................................................. 32
10.17 Total Count2 (TotalCnt[23:16], 0x6072 TotalCnt2) ........................................................... 32
10.18 Total Count3 (TotalCnt[31:24], 0x6073 TotalCnt3) ........................................................... 32
10.19 Load Total Count (Load TotalCnt, 0x6074)........................................................................ 33
10.20 Global Total Count0 (GTotalCnt[7:0], 0x6080 GTotalCnt0) ............................................. 33
10.21 Global Total Count1 (GTotalCnt[15:8], 0x6081 GTotalCnt1) ........................................... 33
10.22 Global Total Count2 (GTotalCnt[23:16], 0x6082 GTotalCnt2) ......................................... 33
10.23 Global Total Count3 (GTotalCnt[31:24], 0x6083 GTotalCnt3) ......................................... 33
11. Electrical Information: .......................................................................................................................................... 33
11.1 Absolute Maximum Ratings................................................................................................ 33
11.2 Recommended Operating Conditions.................................................................................. 33
11.3 General DC Characteristics ................................................................................................. 33
11.4 DC Electrical Characteristics for 3.3V Operation ............................................................... 34
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