5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Table 2: Pin description …continued
I A logic LOW on this pin will transfer the contents of the data bus (D[0:7]) from an external
CPU to an internal register that is deﬁned by address bits A[0:2]. A logic HIGH on this pin
will load the contents of an internal register deﬁned by address bits A[0:2] on the
SC68C2550B data bus (D[0:7]) for access by an external CPU.
O Output 2 (user-deﬁned). This function is associated with individual channels A and B.
The state of these pins is deﬁned by the user through the software settings of MCR.
OP2A/OP2B is a logic 0 when MCR is set to a logic 1. OP2A/OP2B is a logic 1 when
MCR is set to a logic 0. The output of these two pins is HIGH after reset.
I Reset (active LOW). A logic 0 on this pin will reset the internal registers and all the
outputs. The UART transmitter output and the receiver input will be disabled during reset
time. (See Section 7.10 “SC68C2550B external reset condition” for initialization details.)
RXRDYA, 31, 18 O Receive Ready A, B (active LOW). This function is associated with PLCC44 and
LQFP48 packages only. This function provides the RX FIFO/RHR status for individual
receive channels (A-B). RXRDYn is primarily intended for monitoring DMA mode 1
transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to
read/upload, that is, receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed
trigger level has not been reached. This signal can also be used for single mode transfers
(DMA mode 0).
TXRDYA, 43, 6
O Transmit Ready A, B (active LOW). This function is associated with PLCC44 and
LQFP48 packages only. These outputs provide the TX FIFO/THR status for individual
transmit channels (A-B). TXRDYn is primarily intended for monitoring DMA mode 1
transfers for the transmit data FIFOs. An individual channel’s TXRDYA, TXRDYB buffer
ready status is indicated by logic 0, that is, at lease one location is empty and available in
the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no more empty
locations in the FIFO or THR. This signal can also be used for single mode transfers
(DMA mode 0).
Power supply input
Crystal or external clock input. Functions as a crystal input or as an external clock
input. A crystal can be connected between this pin and XTAL2 to form an internal
oscillator circuit. Alternatively, an external clock can be connected to this pin to provide
custom data rates. (See Section 6.5 “Programmable baud rate generator”.) See Figure 3.
O Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator
output or buffered clock output. Should be left open if an external clock is connected to
XTAL1. For extended frequency operation, this pin should be tied to VCC via a 2 kΩ
Carrier Detect (active LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been detected by
the modem for that channel.
Clear to Send (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready
to accept transmit data from the SC68C2550B. Status can be tested by reading MSR.
This pin has no effect on the UART’s transmit or receive operation.
Data Set Ready (active LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem or data set is
powered-on and is ready for data exchange with the UART. This pin has no effect on the
UART’s transmit or receive operation.
9397 750 14941
Product data sheet
Rev. 02 — 28 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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