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Preliminary Technical Data
FEATURES
Complete rate gyroscope on a single chip
±300°/sec angular rate sensing
High vibration rejection over a wide frequency range
Excellent 25°/hr null offset stability
Internally temperature compensated
2000 g powered shock survivability
SPI digital output with 16-bit data-word
Low noise and low power
3.3 V and 5V operation
−40°C to +105°C operation
Ultra small, light, and RoHS compliant
Two package options
Low cost SOIC_CAV package for yaw rate (Z-axis) response
Innovative ceramic vertical mount package, which can be
oriented for pitch, roll, or yaw response
APPLICATIONS
Rotation sensing medical applications
Rotation sensing industrial and instrumentation
High performance platform stabilization
High Performance,www.DataSheet4U.com
Digital Output Gyroscope
ADXRS450
GENERAL DESCRIPTION
The ADXRS450 is an angular rate sensor (gyroscope) intended
for industrial, medical, instrumentation, stabilization, and other
high performance applications. An advanced, differential, quad
sensor design rejects the influence of linear acceleration, enabling
the ADXRS450 to operate in exceedingly harsh environments
where shock and vibration are present.
The ADXRS450 utilizes an internal, continuous self-test archi-
tecture. The integrity of the electromechanical system is checked
by applying a high frequency electrostatic force to the sense
structure to generate a rate signal that can be differentiated from
the baseband rate data and internally analyzed.
The ADXRS450 is capable of sensing angular rate of up to
±300°/sec. Angular rate data is presented as a 16-bit word, as
part of a 32-bit SPI message.
The ADXRS450 is available in a cavity plastic 16-lead SOIC
(SOIC_CAV) and an SMT-compatible vertical mount package
(LCC_V), and is capable of operating across both a wide voltage
range (3.3 V to 5 V) and temperature range (−40°C to +105°C).
CP5
VX
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATION
ADXRS450
Z-AXIS ANGULAR
RATE SENSOR
HV DRIVE
CLOCK
PHASE DIVIDER
LOCKED
LOOP AMPLITUDE
DETECT
BAND-PASS
FILTER
ADC 12
DEMOD
Q DAQ
P DAQ
Q FILTER
ST
CONTROL
ALU
DECIMATION
FILTER
TEMPERATURE
CALIBRATION
FAULT
DETECTION
EEPROM
Figure 1.
LDO
REGULATOR
PDD
DVDD
AVDD
SPI
INTERFACE
MOSI
MISO
SCLK
CS
DVSS
PSS
AVSS
Rev. PrA
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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©2010 Analog Devices, Inc. All rights reserved.

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ADXRS450
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Specifications..................................................................................... 3 
Absolute Maximum Ratings............................................................ 4 
Thermal Resistance ...................................................................... 4 
Rate Sensitive Axis........................................................................ 4 
ESD Caution.................................................................................. 4 
Pin Configurations and Function Descriptions ........................... 5 
Typical Performance Characteristics ............................................. 7 
Theory of Operation ........................................................................ 9 
Continuous Self-Test.................................................................... 9 
Applications Information .............................................................. 10 
Calibrated Performance............................................................. 10 
Mechanical Considerations for Mounting .............................. 10 
Preliminary Technical Datawww.DataSheet4U.com
Applications Circuits ................................................................. 10 
ADXRS450 Signal Chain Timing............................................. 10 
SPI Communication Protocol....................................................... 12 
Command/response................................................................... 12 
SPI Communications Characteristics...................................... 13 
SPI Applications.......................................................................... 14 
SPI Rate Data Format..................................................................... 19 
Memory Map and Registers .......................................................... 20 
Memory Map .............................................................................. 20 
Memory Register Definitions ................................................... 21 
Package Orientation and Layout information............................ 23 
Solder Profile .............................................................................. 25 
Package Marking Codes ............................................................ 26 
Outline Dimensions ....................................................................... 27 
Ordering Guide .......................................................................... 28 
Rev. PrA | Page 2 of 28

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Preliminary Technical Data
ADXRS450www.DataSheet4U.com
SPECIFICATIONS
Specification conditions @ TA = TMIN to TMAX, PDD = 5 V, angular rate = 0°/sec, bandwidth = 80 Hz ±1 g, continuous self-test on.
Table 1.
Parameter
MEASUREMENT RANGE
SENSITIVITY
Nominal Sensitivity
Sensitivity Tolerance
Nonlinearity1
Cross-Axis Sensitivity2
NULL
Null Accuracy
NOISE PERFORMANCE
Rate Noise Density
LOW-PASS FILTER
Cut-Off (−3dB) Frequency
Group Delay3
SHOCK AND VIBRATION IMMUNITY
Sensitivity to Linear Acceleration
Vibration Rectification
SELF-TEST
Magnitude
Fault Register Threshold
Sensor Data Status Threshold
Frequency
ST Low-Pass Filter
−3 dB Frequency
Group Delay3
SPI COMMUNICATIONS
Clock Frequency
Voltage Input High
Voltage Input Low
Output Voltage Low
Output Voltage High
Test Conditions/Comments
Full-scale range
See Figure 2
Best fit straight line
TA = 25°C
f0/200, see Figure 6
f = 0 Hz
DC to 5 kHz
See Continuous Self-Test
Compared to LOCST data
Compared to LOCST data
f0/32
f0/800, see Figure 7
MOSI, CS, SCLK
MOSI, CS SCLK
MISO, current = 3 mA
MISO, current = −2 mA
Symbol
FSR
fLP
tLP
fST
Min
±300
3.25
2239
1279
52
Typ
80
±3
0.05
±3
±3
0.015
80
4
0.03
0.003
2559
500
2
64
0.85 × PDD
−0.3
PDD − 0.5
Max
±400
Unit
°/sec
LSB/°/sec
%
0.25 % FSR rms
%
°/sec
°/sec/√Hz
Hz
4.75 ms
°/sec/g
°/sec/g2
2879
3839
LSB
LSB
LSB
Hz
Hz
76 ms
8.08
PDD + 0.3
PDD × 0.15
0.5
MHz
V
V
V
V
Pull up Current
MEMORY REGISTERS
Temperature Sensor
Value at 45°C
Scale Factor
Quad, ST, Rate, DNC Registers
Scale Factor
POWER SUPPLY
Supply Voltage
Quiescent Supply Current
Turn-On Time
TEMPERATURE RANGE
CS, PDD = 3.3 V, CS = 0.75 × PDD
CS, PDD = 5 V, CS = 0.75 × PDD
See Memory Register Definitions
Power on to 0.5°/sec of final
Independent of package type
PDD 3.15
IDD
TMIN, TMAX
−40
50 200
70 300
μA
μA
0
5
80
5.25
6.0 10.0
100
+105
LSB
LSB/°C
LSB/°/sec
V
mA
ms
°C
1 Maximum limit is guaranteed through ADI characterization.
2 Cross-axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB).
3 Minimum and maximum limits are guaranteed by design.
Rev. PrA | Page 3 of 28

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ADXRS450
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Acceleration (Any Axis, Unpowered, 0.5 ms)
Acceleration (Any Axis, Powered, 0.5 ms)
Supply Voltage (PDD)
Output Short-Circuit Duration (Any Pin to
Ground)
Temperature Range
Operating
LCC_V Package
SOIC_CAV Package
Storage
LCC_V Package
SOIC_CAV Package
Rating
2000 g
2000 g
−0.3 V to +6.0 V
Indefinite
−40°C to +125°C
−40°C to +125°C
−65°C to +150°C
−40°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, for a device
soldered in a printed circuit board (PCB) for surface-mount
packages.
Table 3. Thermal Resistance
Package Type
16-Lead SOIC_CAV
14-Lead Ceramic LCC_V
θJA
191.5
185.5
θJC
25
23
Unit
°C/W
°C/W
Preliminary Technical Datawww.DataSheet4U.com
RATE SENSITIVE AXIS
The ADXRS450 is available in two package options. The
SOIC_CAV package configuration is for applications that
require a Z-axis (yaw) rate sensing device. The device transmits
a positive going LSB count for clockwise rotation about the axis
normal to the package top. Conversely, a negative going LSB
count is transmitted for counterclockwise rotation about the
Z-zxis. The vertical mount package (LCC_V) option is for
applications that require rate sensing in the axes parallel to the
plane of the PCB (pitch and roll). The same principles of LSB
count transmission for clockwise and counterclockwise rotation
about the parallel axes apply to the LCC_V option. See Figure 2
for details.
RATE
AXIS
Z-AXIS
LONGITUDINAL
AXIS
+
7
1
A1 A B C D E F G
LATERAL AXIS
RATE
AXIS
+8
17
VMP PACKAGE
Figure 2. Rate Signal Increases with Clockwise Rotation
ESD CAUTION
Rev. PrA | Page 4 of 28

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Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DVDD 1
RSVD 2
16 SCLK
15 MOSI
RSVD 3
CS 4
MISO 5
ADXRS450
TOP VIEW
(Not to Scale)
14 AVDD
13 DVSS
12 RSVD
PDD 6
PSS 7
VX 8
11 AVSS
10 RSVD
9 CP5
Figure 3. SOIC_CAV Pin Configuration
ADXRS450www.DataSheet4U.com
Table 4. 14-Lead SOIC_CAV Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DVDD
Digital Regulated Voltage. See Figure 21 for the applications circuit diagram.
2
RSVD
Reserved. This pin must be connected to DVSS.
3 NC Reserved. This pin must be connected to DVSS.
4 CS Chip Select.
5
MISO
Master In/Slave Out.
6 PDD Supply Voltage.
7 PSS Switching Regulator Ground.
8 VX High Voltage Switching Node. See Figure 21 for the applications circuit diagram.
9 CP5 High Voltage Supply. See Figure 21 for the applications circuit diagram.
10 NC Reserved. This pin must be connected to DVSS.
11
AVSS
Analog Ground.
12 NC Reserved. This pin must be connected to DVSS.
13
DVSS
Digital Signal Ground.
14
AVDD
Analog Regulated Voltage. See Figure 21 for the applications circuit diagram.
15
MOSI
Master Out/Slave In.
16
SCLK
SPI Clock.
Rev. PrA | Page 5 of 28