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Intel® EP80579 Integrated Processor
Product Line
Datasheet
Order Number: 320066-003US
August 2009

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INFORMATIONLegal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
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Copyright © 2009, Intel Corporation. All Rights Reserved.
Intel® EP80579 Integrated Processor Product Line Datasheet
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Product Features
„ System on a Chip (SoC)
— Integrated Intel® Architecture (IA) processor
and chipset (MCH/ICH) technology
— Extensive integration of standard Intel
architecture communications interfaces
provide cost, power and board area savings
(Gigabit Ethernet (GbE), Time Division
Multiplexing (TDM)processing, Security
Services Unit (SSU),and Acceleration
Services Units (ASU))
„ SKU Support1
— Embedded: Intel architecture compatibility
and high-speed interfaces (GbEs, PCI
Express*)
— Application Services: Security — Packet
security compatibility and IP Telephony packet
security, TDM, and High-Level Data Link
Control (HDLC)
„ Intel Architecture Processor
— Low-power and high-performance architecture
based on Intel Architecture (IA-32) processor
— Three operating frequency SKUs:
- 600 MHz, 1066 MHz, or 1200 MHz
— 256 KB L2 data coherent cache (2 way)
„ Integrated Memory Control Hub (IMCH) and
Integrated I/O Control Hub (IICH) Compatible
— Enhanced DMA (EDMA) controller
— Two SATA Gen1 or Gen2 interfaces
— Two USB 1.1 or USB 2.0 ports
— Two integrated, 16550-compatible UARTs
— LPC 1.1 interface
— Serial Peripheral Interface (SPI)
— Two SMBus 2.0 compliant interfaces
— GPIOs
— Watchdog Timer
— One 32/64-bit and two 32-bit high-precision
event timers
„ Acceleration Services Unit (ASU)
— High performance accelerator on-chip engines
for packet processing
— Support capabilities for commonly used
protocol implementations such as TCP/IP, UDP,
IPSec, SSL, NAT, and SRTP
„ Security Services Unit (SSU)
— High-performance on-chip Crypto Accelerator
— Support capabilities for commonly used
cryptographic protocol implementations
„ Single-Channel Double-Data-Rate (DDR)
SDRAM Memory
— Supports DDR2 at 400/533/667/800 MT/s
— Supports 32 or 64-bit interfaces
— Error correction code (ECC); single-bit correct/
double-bit detect (SEC/DED) coverage
— Addressable from Intel architecture processor
and PCI Express
„ Three Gigabit Ethernet MACs
— Three 10/100/1000 ports with RGMII/RMII
interfaces
— MDIO interface for external PHY configuration
— Serial EEPROM interface supports network
boot and wake-on LAN
„ Industry Standard PCI Express Interface
— Supports 1x8, 2x4, or 2x1 configurations as a
root complex
„ Integrated Serial ATA (SATA) Host Controllers
— Independent DMA operation on two ports
— Data transfer rates up to 3.0 Gb/s
— Alternate Device ID
„ Integrated High-speed Serial Interface (TDM)
— Supports up to 12 external T1/E1 and codecs
— Supports up to 128 HDLC channels
„ Local Expansion Bus (LEB)
— Supports up to eight chip selects
— 25-bit address and 16-bit data
— Supports HPI-8 and HPI-16
„ Dual Controller Area Network (CAN)
— Supports two CAN 2.0b interfaces
„ Single Synchronous Serial Port (SSP)
Compatible
„ IEEE 1588-2008 Hardware Assistance
— Supports two GbE and two CAN interfaces
— Time master/target support
„ 1088-Ball FCBGA package
— Dimensions of 37.5 mm x 37.5 mm
— 1.092-mm solder ball pitch
— Lead-free only — RoHS 5/6 compliant
„ Typical Applications
— Embedded, Security and/or IP Telephony
applications
† Intel recommends using the SPI for Pre-boot firmware
due to the reduced availability of LPC FWH.
‡ Feature must be enabled with EP80579 software. Refer
to the EP80579 software documentation for more
information.
1. For complete information about product features and SKUs, please refer to Chapter 47.0, “SKUs, Power Savings and Pre-Boot
Firmware”.
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
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Contents
Contents
Introduction and Overview, Volume 1 of 6 ................................... 91
1.0 Introduction ............................................................................................................93
1.1 Introduction ......................................................................................................93
1.2 Document Organization ......................................................................................93
1.3 Referenced Documents and Related Websites ........................................................94
1.4 Acronyms .........................................................................................................95
1.5 Glossary ...........................................................................................................98
2.0 Architectural Overview .......................................................................................... 103
2.1 Overview ........................................................................................................ 103
2.1.1 Block Summary ...................................................................................... 103
2.1.2 External Interfaces ................................................................................. 106
2.1.3 Frequencies and Gear Ratios .................................................................... 107
2.2 Signaling Architecture ...................................................................................... 107
2.3 DMA and Peer-to-Peer Data Transfers................................................................. 109
3.0 Platform Memory and Device Configuration ........................................................... 111
3.1 Overview ........................................................................................................ 111
3.1.1 Configuration Objectives.......................................................................... 111
3.1.2 Terminology and Conventions .................................................................. 112
3.2 IA Platform Infrastructure ................................................................................. 113
3.2.1 IA Platform View of Endianness ................................................................ 113
3.2.2 IA Platform View of Configuration ............................................................. 114
3.3 High-Level Views ............................................................................................. 116
3.3.1 Characteristics of External System Memory (DRAM) .................................... 116
3.3.2 Characteristics of Internal and External Memories ....................................... 117
3.3.3 Characteristics of Device Configuration ...................................................... 118
3.4 Memory Map for IA-Attached Agents .................................................................. 119
3.5 Memory Map for AIOC-Attached Devices ............................................................. 119
3.6 Endianness ..................................................................................................... 119
3.7 PCI Configuration............................................................................................. 119
3.7.1 Overview............................................................................................... 120
3.7.2 Device Tree ........................................................................................... 121
3.7.3 Materializing Device Structures................................................................. 124
3.7.4 PCI Configuration Headers ....................................................................... 124
4.0 Signaling................................................................................................................ 131
4.1 Overview ........................................................................................................ 131
4.1.1 Terminology and Conventions .................................................................. 132
4.2 Existing Signaling Capabilities............................................................................ 132
4.2.1 IA-32 core/Platform ................................................................................ 133
4.2.1.1
4.2.1.2
MSI and INTx Signaling.................................................................... 133
GPIO Signaling ............................................................................... 133
4.2.2 Other Agents ......................................................................................... 133
4.3 Inter-Agent Signaling ....................................................................................... 134
4.3.1 Signaling that Travels Around the Signal Bridge .......................................... 135
4.3.2 Signaling that is Bridged from a Side-Band Source Signal ............................ 135
4.3.2.1 Targeting the IA-32 core with a Bridged Signal.................................... 136
5.0 Error Handling ....................................................................................................... 139
5.1 Overview ........................................................................................................ 139
5.2 EP80579 View of Error Reporting ....................................................................... 139
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5.2.1 Hardware Capabilities ............................................................................. 139
5.2.2 Software Usage Model ............................................................................ 141
5.3 Error Reporting by the IMCH ............................................................................. 141
5.3.1 Overview of the First and Next Error Architecture ....................................... 141
5.3.2 Global Error Events ................................................................................ 142
5.3.3 Unit-Level Errors from the Buffer Unit ....................................................... 143
5.3.4 Unit-Level Errors from the DRAM Interface ................................................ 143
5.3.5 Unit-Level Errors from the FSB Interface ................................................... 144
5.3.6 Unit-Level Errors from the NSI ................................................................. 145
5.3.7 Unit-Level Errors from the EDMA Engine.................................................... 146
5.3.8 Unit-Level Errors from PCI Express* Ports A0 and A1 .................................. 147
5.4 Error Reporting by the IICH .............................................................................. 149
5.4.1 SMBus Interface .................................................................................... 149
5.4.2 LPC Interface......................................................................................... 150
5.4.3 USB 1.1 Interface .................................................................................. 151
5.4.4 USB 2.0 Interface .................................................................................. 151
5.4.5 SATA Interface ...................................................................................... 152
5.4.6 Serial I/O Interface ................................................................................ 153
5.5 Error Reporting by the System Memory Controller ............................................... 153
5.5.1 Handling Out-of-Bounds Addresses........................................................... 154
5.5.2 IMCH - Memory Controller ....................................................................... 154
5.6 Error Reporting by AIOC Devices ....................................................................... 155
5.6.1 Gigabit Ethernet MAC ............................................................................. 155
5.6.2 CAN Interface ........................................................................................ 156
5.6.3 SSP Interface ........................................................................................ 157
5.6.4 Local Expansion Bus ............................................................................... 158
5.6.5 IEEE 1588, and GCU............................................................................... 159
6.0 Reset and Power Management............................................................................... 161
6.1 Reset and Powergood Distribution ..................................................................... 161
6.1.1 Types of Reset....................................................................................... 161
6.1.1.1
6.1.1.2
6.1.1.3
6.1.1.4
6.1.1.5
6.1.1.6
Powergood Implementation.............................................................. 161
Hard Reset Implementation.............................................................. 162
Software Controlled Reset................................................................ 162
CPU Only Reset Implementation ....................................................... 162
S-state Wake Events ....................................................................... 163
Targeted Reset Implementation ........................................................ 163
6.1.2 Platform Reset and Powergood................................................................. 163
6.1.2.1
6.1.2.2
6.1.2.3
Platform Powergood ........................................................................ 163
Platform Reset................................................................................ 163
Reset and Powergood Distribution ..................................................... 164
6.1.3 EP80579 Power Sequencing and Reset Sequence........................................ 167
6.2 BIOS Boot Flow (Initialization) .......................................................................... 175
6.2.1 Memory Configuration............................................................................. 176
6.2.2 Memory Initialization .............................................................................. 176
6.2.3 Boot from Network ................................................................................. 176
6.3 Power Management ......................................................................................... 177
6.3.1 Power Management States ...................................................................... 177
6.3.2 Power Management Support .................................................................... 179
6.3.2.1
6.3.2.2
Transitioning Between Power States .................................................. 181
Power State Transition Timing Diagrams ............................................ 181
6.3.3 Thermal Sensor ..................................................................................... 182
6.3.4 ACPI Implementation.............................................................................. 182
7.0 Register Summary ................................................................................................. 183
7.1 Overview of Register Descriptions and Summaries ............................................... 183
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
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