FSEZ1307.pdf 데이터시트 (총 16 페이지) - 파일 다운로드 FSEZ1307 데이타시트 다운로드

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February 2010
FSEZ1307
Primary-Side-Regulation PWM with Power MOSFET
Integrated
Features
ƒ Low Standby Power: Under 30mW
ƒ High-Voltage Startup
ƒ Few External Components
ƒ Constant-Voltage (CV) and Constant-Current (CC)
Control without Secondary-Feedback Circuitry
ƒ Green Mode: Linearly Decreasing PWM Frequency
ƒ Fixed PWM Frequency at 50kHz with Frequency
Hopping to Solve EMI Problem
ƒ Cable Compensation in CV Mode
ƒ Peak-Current-Mode Control in CV Mode
ƒ Cycle-by-Cycle Current Limiting
ƒ VDD Over-Voltage Protection with Auto Restart
ƒ VDD Under-Voltage Lockout (UVLO)
ƒ Gate Output Maximum Voltage Clamped at 15V
ƒ Fixed Over-Temperature Protection with
Auto Restart
ƒ Available in 7-Lead SOP Package
Description
This third-generation Primary Side Regulation (PSR)
PWM controller combination power MOSFET,
FSEZ1307, provides several features to enhance the
performance of low-power flyback converters. The
proprietary topology, TRUECURRENT™, enables
precise CC regulation and simplified circuit design for
battery-charger applications. Compared to a
conventional design or a linear transformer, a low-cost,
smaller, and lighter charger results.
To minimize standby power consumption, the
proprietary green mode provides off-time modulation to
linearly decrease PWM frequency under light-load
conditions. Green mode assists the power supply in
meeting power conservation requirements.
By using the FSEZ1307, a charger can be implemented
with few external components and minimized cost. A
typical output CV/CC characteristic envelope is shown
in Figure 1.
Applications
ƒ Battery chargers for cellular phones, cordless
phones, PDA, digital cameras, power tools, etc.
ƒ Replaces linear transformers and RCC SMPS
Figure 1. Typical Output V-I Characteristic
Ordering Information
Part Number
Operating
Temperature Range
FSEZ1307MY
-40°C to +105°C
Eco
Status
Green
Package
Packing
Method
7-Lead, Small Outline Package (SOP-7) Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2010 Fairchild Semiconductor Corporation
FSEZ1307 • Rev. 1.0.2
www.fairchildsemi.com

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Application Diagram
AC
Input
D1
RF
D2
L1
D4
C1
D3
C2
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Rsn2
Csn
Rsn1 Dsn
Rsn Csn2
T1
DF
DC
CO1 CO2 Rd Output
DFa
CVDD
2 VDD
7 HV
3 GND
VS 5
DRAIN 8
CS 1
COMR 4
CVS
CCR
R1
R2
RSENSE
Internal Block Diagram
Figure 2. Typical Application
© 2010 Fairchild Semiconductor Corporation
FSEZ1307 • Rev. 1.0.2
Figure 3. Functional Block Diagram
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Marking Information
Pin Configuration
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F: Fairchild Logo
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M=SOP)
P: Y=Green Package
M: Manufacture Flow Code
Figure 4. Top Mark
Figure 5. Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
7
8
Name
CS
VDD
GND
COMR
VS
HV
DRAIN
Description
Current Sense. This pin connects a current-sense resistor to detect the MOSFET current for
peak-current-mode control in CV mode and provides the output-current regulation in CC mode.
Power Supply. IC operating current and MOSFET driving current are supplied using this pin.
This pin is connected to an external VDD capacitor of typically 10µF. The threshold voltages for
startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA.
Ground
Cable Compensation. This pin connects a 1µF capacitor between the COMR and GND pins
for compensation voltage drop due to output cable loss in CV mode.
Voltage Sense. This pin detects the output voltage information and discharge time based on
voltage of auxiliary winding.
High Voltage. This pin connects to a bulk capacitor for high-voltage startup.
Driver Output. Power MOSFET drain. This pin is the high-voltage power MOSFET drain.
© 2010 Fairchild Semiconductor Corporation
FSEZ1307 • Rev. 1.0.2
3
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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min. Max. Units
VHV
VVDD
VVS
VCS
VCOMV
VCOMI
VDS
ID
IDM
EAS
IAR
PD
θJA
HV Pin Input Voltage
DC Supply Voltage(1,2)
VS Pin Input Voltage
CS Pin Input Voltage
Voltage Error Amplifier Output Voltage
Current Error Amplifier Output Voltage
Drain-Source Voltage
Continuous Drain Current
Pulsed Drain Current
TA=25°C
TA=100°C
Single Pulse Avalanche Energy
Avalanche Current
Power Dissipation (TA50°C)
Thermal Resistance (Junction to Air)
500 V
30 V
-0.3 7.0
V
-0.3 7.0
V
-0.3 7.0
V
-0.3 7.0
V
700 V
0.5 A
0.35 A
3.5 A
35 mJ
1A
660 mW
150 °C/W
θJC Thermal Resistance (Junction to Case)
39 °C/W
TJ
TSTG
TL
ESD
Operating Junction Temperature
Storage Temperature Range
Lead Temperature (Wave Soldering or IR, 10 Seconds)
Electrostatic Discharge
Capability
Human Body Model (Except HV Pin),
JEDEC-JESD22_A114
Charged Device Model (Except HV Pin),
JEDEC-JESD22_C101
-40
-55
+150
+150
+260
2500
1250
°C
°C
°C
V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to the GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
TA Operating Ambient Temperature
Min.
-40
Max.
+105
Units
°C
© 2010 Fairchild Semiconductor Corporation
FSEZ1307 • Rev. 1.0.2
4
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Electrical Characteristics
Unless otherwise specified, VDD=15V and TA=25.
Symbol
Parameter
VDD Section
VOP Continuously Operating Voltage
VDD-ON Turn-On Threshold Voltage
VDD-OFF Turn-Off Threshold Voltage
IDD-OP
Operating Current
IDD-GREEN Green-Mode Operating Supply Current
VDD-OVP VDD Over-Voltage-Protection Level (OVP)
VDD-OVP-HYS Hysteresis Voltage for VDD OVP
tD-VDDOVP VDD Over-Voltage-Protection Debounce Time
HV Startup Current Source Section
VHV-MIN Minimum Startup Voltage on HV Pin
IHV Supply Current Drawn from HV Pin
IHV-LC
Leakage Current after Startup
Oscillator Section
fOSC Frequency
Center Frequency
Frequency Hopping Range
fOSC-N-MIN Minimum Frequency at No-Load
fOSC-CM-MIN Minimum Frequency at CCM
fDV Frequency Variation vs. VDD Deviation
fDT Frequency Variation vs. Temperature Deviation
Voltage-Sense Section
Itc IC Bias Current
VBIAS-COMV Adaptive Bias Voltage Dominated by VCOMV
Current-Sense Section
tPD Propagation Delay to GATE Output
tMIN-N
VTH
Minimum On Time at No-Load
Threshold Voltage for Current Limit
Voltage-Error-Amplifier Section
VVR Reference Voltage
VN Green-Mode Starting Voltage on EA_V
VG Green-Mode Ending Voltage on EA_V
Current-Error-Amplifier Section
VIR Reference Voltage
Cable Compensation Section
VCOMR COMR Pin for Cable Compensation
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Conditions Min. Typ. Max. Units
23 V
15 16 17
V
4.5 5.0 5.5
V
2.5 5.0 mA
0.95 1.20 mA
24 V
1.5 2.0 2.5
V
50 200 300 µs
VDC=100V
HV=500V,
VDD= VDD-
OFF+1V
50 V
1.5 3.0 mA
0.96 3.00 µA
47 50 53
kHz
±1.5 ±2.0 ±2.5
370 Hz
13 kHz
VDD=10~25V,
1 2%
TA=-40°C to
105°C
15 %
RVS=20k
10 µA
1.4 V
90 200 ns
700 850 1050 ns
0.8 V
fOSC-2kHz
fOSC=1kHz
2.475
2.500
2.5
0.4
2.525
V
V
V
2.475 2.500 2.525 V
0.75 V
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FSEZ1307 • Rev. 1.0.2
5
www.fairchildsemi.com