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CS42L73
Ultralow Power Mobile Audio and Telephony CODEC
Product Overview
Stereo analog-to-digital converter (ADC)
Dual analog or digital mic support
Dual mic bias generators
Four digital-to-analog converters (DACs)
coupled to five outputs
– Ground-centered stereo headphone amp.
– Ground-centered stereo line output
– Mono ear speaker amplifier
– Mono 1-W speakerphone amplifier
– Mono speakerphone line output for stereo
speakerphone expansion
Three serial ports with asynchronous sample
rate converters
Digital audio mixing and routing
Ultralow Power Consumption
3.8-mW quiescent headphone playback
Applications
Smart phones, ultramobile PCs, and mobile
Internet devices
System Features
Native (no PLL required) support for 6/12/
24 MHz, 13/26 MHz, and 19.2/38.4 MHz
master clock rates and typical audio clock rates
Integrated high-efficiency power management
reduces power consumption
– Internal LDO regulator to reduce internal
digital operating voltage to VL/2 V
– Step-down charge pump provides low
headphone/line out supply voltage
– Inverting charge pump accommodates low
system voltage by providing negative rail for
HP and line amplifier
Flexible speakerphone amplifier powering
– 3.00–5.25 V range
– Independent cycling
Power-down management
– Individual controls for ADCs, digital mic
interface, mic bias generators, serial ports,
and output amplifiers and associated DACs
Programmable thermal overload notification
High-speed I²C™ control port (400 kHz)
(Features continued on page 2)
VL VD_FILT
MCLK1
MCLK2
LDO
VD_FILT
MCLK
Control Port
Auxiliary Serial Port
Audio Serial Port
Voice Serial Port
Digital MIC Interface
Control Port
Auxiliary
Serial Port
SDIN
ASRC
ASRC
SDOUT
Audio
Serial Port
SDIN
ASRC
ASRC
SDOUT
Voice
Serial Port
SDIN
ASRC
ASRC
SDOUT
Digital MIC Interface
VA
VA CS42L73
Digital Processing
Digital Mixer
MIC/Line Input Path
Auxiliary Serial Port
Audio Serial Port
`+
Voice Serial Port
VCP +VCP_FILT -VCP_FILT
Step-Down
Inverting
Volume, Mute, Limiter
Volume, Mute, Limiter
+VCP_FILT
-VCP_FILT
MCLK
Stereo
Multi-bit
 DAC
+VCP_FILT
-
+
-VCP_FILT
+VCP_FILT
-
+
-VCP_FILT
MCLK
Stereo
Multi-bit
 DAC
VA
B
VP
A
VP
B
Decimator,
HPF,
Noise
Gate,
ALC,
Volume,
Mute,
Swap/Mono
MCLK
Stereo
Multi-bit
 ADC
+
-
-6 to +12 dB,
0.5 dB steps
VP
MIC Bias
MIC Bias Short Detect
+10 or
+20 dB
+
-
+
-
+10 or
+20 dB
Headphone Outputs
Pseudo Diff. Input
Line Outputs
Pseudo Diff. Input
+
-
Ear
Speaker
Output
VP
+ Speakerphone Output
- (Left)
+ Speakerphone Line
- Output (Right)
Line Input (Left)
Pseudo Diff. Input
Line Input (Right)
MIC 1
Pseudo Diff. Input
MIC 2
Pseudo Diff. Input
MIC 1 Bias MIC 2 Bias MIC2_SDET
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2013
(All Rights Reserved)
JULY '13
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Stereo Analog-to-Digital Features
91-db dynamic range (A-weighted)
-85 dB THD+N
Independent ADC channel control
2:1 stereo analog input MUX
Stereo line input: Shared pseudodifferential
reference input
Dual analog mic inputs
– Pseudodifferential or single-ended
– Two, independent, programmable, low-noise
mic bias outputs
– Mic short detect to support headset button
Analog programmable gain amplifier (PGA)
(+12 to -6 dB in 0.5 dB steps)
+10 dB or +20 dB analog mic boost in addition
to PGA gain settings
Programmable automatic level control (ALC)
– Noise gate for noise suppression
– Programmable threshold and attack/release
rates
Dual Digital Microphone Interface
Programmable clock rate: Integer divide by 2 or
4 of internal MCLK
Stereo DAC to Headphone Amplifier
94-dB dynamic range (A-weighted)
-81 dB THD+N into 32
Integrated step-down/inverting charge pump
Class H amplifier, automatic supply adjustment
– High efficiency
– Low EMI
Pseudodifferential ground-centered outputs
High HP power output at -70/-81 dB THD+N
– 2 x 16/8.1 mW into 16/32 @ 1.8 V
Pop and click suppression
Analog volume control (+12 to -50 dB in 1 dB
steps; to -76 dB in 2 dB steps) with zero-cross
transitions
Digital volume control (+12 to -102 dB in 0.5 dB
steps) with soft-ramp transitions
Programmable peak-detect and limiter
Stereo DAC to Line Outputs
97 dB dynamic range (A-weighted)
-86 dB THD+N
Class-H amplifier
Pseudodifferential ground-centered outputs
1-VRMS line output @ 1.8 V
Pop and click suppression
Analog volume control (+12 to -50 dB in 1 dB
CS42L73
steps; to -76 dB in 2 dB steps) with zero-cross
transitions
Digital volume control (+12 to -102 dB in 0.5 dB
steps) with soft-ramp transitions
Programmable peak-detect and limiter
Mono DAC to Ear Speaker Amplifier
High-power output at -70 dB (0.032%) THD+N:
45 mW into 16 @ 1.8 V
Pop and click suppression
Digital volume control (+12 to -102 dB in 0.5 dB
steps) with soft-ramp transitions
Programmable peak-detect and limiter
Mono DAC to Speakerphone Amplifier
High output power at 1% THD+N: 1.06/0.76/
0.59 W into 8 @ 5.0/4.2/3.7 V
Direct battery-powered operation
Pop and click suppression
Digital volume control (+12 to -102 dB in 0.5 dB
steps) with soft-ramp transitions
Programmable peak-detect and limiter
Mono DAC-to-Speakerphone Line
Output
84 dB dynamic range (A-weighted)
-65 dB THD+N
High voltage (2 VRMS @ VA = 1.8 V, VP =
3.7 V) line output to ensure maximum output
from a wide variety of external amplifiers
Pop and click suppression
Digital volume control (+12 to -102 dB in 0.5 dB
steps) with soft-ramp transitions
Programmable peak-detect and limiter
Serial Ports
Three independent serial ports: auxiliary serial
port (XSP), audio serial port (ASP), and voice
serial port (VSP)
8.00, 11.025, 12.00, 16.00, 22.05, 24.00,
32.00, 44.10, and 48.00 kHz sample rates
All ports support master or slave operation with
I²S interface
XSP and VSP support slave operation with
PCM interface
XSP and ASP are stereo-input/stereo-output
to/from digital mixer
VSP is mono-input/stereo-output to/from digital
mixer
Integrated asynchronous sample rate
converters
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CS42L73
General Description
The CS42L73 is a highly integrated, low-power, audio and telephony CODEC for portable applications such as
smartphones and ultramobile personal computers.
The CS42L73 features a flexible clocking architecture, allowing the device to use reference clock frequencies of
6, 12, 24, 13, 26, 19.2, or 38.4 MHz, or any standard audio master clock. As many as two reference/master clock
sources may be connected; either one can be selected to drive the internal clocks and processing rate of the
CS42L73. Thus, multiple master clock sources within a system can be dynamically activated and deactivated to
minimize system-level power consumption.
Three asynchronous bidirectional serial ports (auxiliary, audio, and voice serial ports (XSP, ASP, and VSP,
respectively) support multiple clock domains of various digital audio sources or destinations. Three low-latency,
fast-locking, integrated high-performance asynchronous sample rate converters synchronize and convert the
audio samples to the internal processing rate of the CS42L73.
A stereo line input or two mono (one stereo) mic inputs are routed to a stereo ADC. The mic inputs may be
selectively preamplified by +10 or +20 dB. Two independent, low-noise mic bias voltage supplies are also provided.
A PGA is applied to the inputs before they reach the ADC.
The stereo input path that follows the stereo ADC begins with a multiplexer to selectively choose data from a
digital mic interface. Following the multiplexer, the data is decimated, selectively DC high-pass filtered,
channel-swapped or mono-to-stereo routed (fanned-out), and volume adjusted or muted. The volume levels can be
automatically adjusted via a programmable ALC and noise gate.
A digital mixer is used to mix and route the CS42L73’s inputs (analog inputs to ADC, digital mic, or serial ports) to
outputs (DAC-fed amplifiers or serial ports). There is independent attenuation on each mixer input for each output.
The processing along the output paths from the digital mixer to the two stereo DACs includes volume adjustment
and mute control. A peak-detector can be used to automatically adjust the volume levels via a programmable limiter.
The first stereo DAC feeds the stereo headphone and line output amplifiers, which are powered from a dedicated
positive supply. An integrated charge pump provides a negative supply. This allows a ground-centered analog
output with a wide signal swing, and eliminates external DC-blocking capacitors while reducing pops and clicks.
Tri-level Class H amplification is used to reduce power consumption under low-signal-level conditions. Analog
volume controls are provided on the stereo headphone and line outputs.
The second stereo DAC feeds several mono outputs. The left channel of the DAC sources a mono,
differential-drive, speakerphone amplifier for driving the handset speakerphone. The right channel sources a
mono, differential-drive, earphone amplifier for driving the handset earphone. The right channel is also routed to
a mono, differential-drive, speakerphone line output, which may be connected to an external amplifier to
implement a stereo speakerphone configuration when it is used in conjunction with the integrated speakerphone
amplifier.
The CS42L73 implements robust power management to achieve ultralow power consumption. High granularity in
power-down controls allows individual functional blocks to be powered down when unused. The internal low-dropout
regulator (LDO) saves power by running the internal digital circuits at half the logic interface supply voltage (VL/2).
A high-speed I2C control port interface capable of up to 400 kHz operation facilitates register programming.
The CS42L73 is available in space-saving 64-ball WLCSP and 65-ball FBGA packages for the commercial (-40° to
+85° C) grade.
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CS42L73
TABLE OF CONTENTS
1. PACKAGE PIN/BALL ASSIGNMENTS AND CONFIGURATIONS ..................................................... 12
1.1 64-Ball Wafer-Level Chip Scale Package (WLCSP) ...................................................................... 12
1.2 65-Ball Fine-Pitch Ball Grid Array (FBGA) Package ...................................................................... 13
1.3 Pin/Ball Descriptions ...................................................................................................................... 14
1.4 Digital Pin/Ball I/O Configurations .................................................................................................. 16
2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 17
2.1 Low-Profile Charge-Pump Capacitors ........................................................................................... 18
2.2 Ceramic Capacitor Derating ........................................................................................................... 18
3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 19
4. APPLICATIONS ................................................................................................................................... 41
4.1 Overview ........................................................................................................................................ 41
4.1.1 Basic Architecture ................................................................................................................. 41
4.1.2 Line and Microphone Inputs .................................................................................................. 41
4.1.3 Line and Headphone Outputs (Class H, Ground-Centered Amplifiers) ................................. 41
4.1.4 Digital Mixer ........................................................................................................................... 41
4.1.5 Power Management .............................................................................................................. 41
4.2 Internal Master Clock Generation .................................................................................................. 42
4.3 Thermal Overload Notification ....................................................................................................... 42
4.4 Pseudodifferential Outputs ............................................................................................................. 43
4.5 Class H Amplifier .......................................................................................................................... 44
4.5.1 Power Control Options .......................................................................................................... 44
4.5.1.1 Standard Class AB Operation (Mode 001, 010, and 011) ......................................... 45
4.5.1.2 Adapt-to-Volume Settings (Mode 000) ...................................................................... 45
4.5.1.3 Adapt-to-Output Signal (Mode 111) ........................................................................... 46
4.5.2 Power Supply Transitions ...................................................................................................... 46
4.5.3 Efficiency ............................................................................................................................... 49
4.6 DAC Limiter .................................................................................................................................... 49
4.7 Analog Output Current Limiter ....................................................................................................... 51
4.8 Serial Ports .................................................................................................................................... 51
4.8.1 Power Management .............................................................................................................. 51
4.8.2 I/O .......................................................................................................................................... 51
4.8.3 High-impedance Mode .......................................................................................................... 52
4.8.4 Master and Slave Timing ....................................................................................................... 52
4.8.4.1 SCLK = MCLK Modes ............................................................................................... 53
4.8.5 Serial Port Sample Rates and Master Mode Settings ........................................................... 53
4.8.6 Formats ................................................................................................................................. 54
4.8.6.1 I²S Format .................................................................................................................. 55
4.8.6.2 PCM Format .............................................................................................................. 55
4.8.7 Mono/Stereo .......................................................................................................................... 57
4.8.8 Data Bit Depths ..................................................................................................................... 57
4.8.8.1 I²S Format Bit Depths ................................................................................................ 57
4.8.8.2 PCM Format Bit Depths ............................................................................................. 58
4.9 Asynchronous Sample Rate Converters (ASRCs) ......................................................................... 59
4.10 Input Paths ................................................................................................................................... 59
4.10.1 Input Path Source Selection and Powering ......................................................................... 59
4.10.2 Digital Microphone (DMIC) Interface ................................................................................... 60
4.10.2.1 DMIC Interface Description ...................................................................................... 60
4.10.2.2 DMIC Interface Signaling ......................................................................................... 60
4.10.2.3 DMIC Interface Powering ......................................................................................... 60
4.10.2.4 DMIC Interface Clock Generation ............................................................................ 61
4.11 Digital Mixer ................................................................................................................................. 61
4.11.1 Mono and Stereo Paths ....................................................................................................... 63
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CS42L73
4.11.2 Mixer Input Attenuation Adjustment .................................................................................... 63
4.11.3 Powered-Down Mixer Inputs ............................................................................................... 64
4.11.4 Avoiding Mixer Clipping ....................................................................................................... 64
4.11.5 Mixer Attenuation Values .................................................................................................... 65
4.12 Recommended Operating Procedures ........................................................................................ 65
4.12.1 Initial Power-Up Sequence .................................................................................................. 65
4.12.2 Power-Up Sequence (xSP to HP/LO) ................................................................................. 66
4.12.3 Power-Down Sequence (xSP to HP/LO) ............................................................................. 67
4.12.4 Recommended Sequence for Modification of the MCLK Signal ......................................... 67
4.12.5 Microphone Enabling/Switching Sequence ......................................................................... 68
4.12.6 Final Power-Down Sequence .............................................................................................. 68
4.13 Using MIC2_SDET as Headphone Plug Detect ........................................................................... 69
4.14 Headphone Plug Detect and Mic Short Detect ............................................................................ 70
4.15 Interrupts ...................................................................................................................................... 70
4.16 Control Port Operation ................................................................................................................. 71
4.16.1 I²C Control ........................................................................................................................... 71
4.17 Fast Start Mode ........................................................................................................................... 73
4.18 Headphone High-Impedance Mode ............................................................................................. 75
5. REGISTER QUICK REFERENCE ........................................................................................................ 76
6. REGISTER DESCRIPTION .................................................................................................................. 81
6.1 Fast Mode Enable (Address 00h) .................................................................................................. 81
6.1.1 Test Bits ................................................................................................................................ 81
6.2 Device ID A and B (Address 01h), C and D (Address 02h), and E (Address 03h) (Read Only) . 81
6.2.1 Device I.D. (Read Only) ........................................................................................................ 81
6.3 Revision ID (Address 05h) (Read Only) ......................................................................................... 81
6.3.1 Alpha Revision (Read Only) .................................................................................................. 81
6.3.2 Metal Revision (Read Only) .................................................................................................. 81
6.4 Power Control 1 (Address 06h) ...................................................................................................... 82
6.4.1 Power Down ADC x ............................................................................................................... 82
6.4.2 Power Down Digital Mic x ...................................................................................................... 82
6.4.3 Discharge Filt+ Capacitor ...................................................................................................... 82
6.4.4 Power Down Device .............................................................................................................. 82
6.5 Power Control 2 (Address 07h) ...................................................................................................... 83
6.5.1 Power Down MICx Bias ......................................................................................................... 83
6.5.2 Power Down VSP .................................................................................................................. 83
6.5.3 Power Down ASP SDOUT Path ............................................................................................ 83
6.5.4 Power Down ASP SDIN Path ................................................................................................ 83
6.5.5 Power Down XSP SDOUT Path ............................................................................................ 83
6.5.6 Power Down XSP SDIN Path ................................................................................................ 83
6.6 Power Control 3 and Thermal Overload Threshold Control (Address 08h) ................................... 84
6.6.1 Thermal Overload Threshold Settings ................................................................................... 84
6.6.2 Power Down Thermal Sense ................................................................................................. 84
6.6.3 Power Down Speakerphone Line Output .............................................................................. 84
6.6.4 Power Down Ear Speaker ..................................................................................................... 84
6.6.5 Power Down Speakerphone .................................................................................................. 84
6.6.6 Power Down Line Output ...................................................................................................... 85
6.6.7 Power Down Headphone ...................................................................................................... 85
6.7 Charge Pump Frequency and Class H Configuration (Address 09h) ............................................ 85
6.7.1 Charge Pump Frequency ...................................................................................................... 85
6.7.2 Adaptive Power Adjustment .................................................................................................. 85
6.8 Output Load, Mic Bias, and MIC2 Short Detect Configuration (Address 0Ah) ............................... 86
6.8.1 VP Supply Minimum Voltage Setting ..................................................................................... 86
6.8.2 Speakerphone Light Load Mode Enable ............................................................................... 86
6.8.3 Mic Bias Output Control ........................................................................................................ 86
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