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N02L63W3Awww.DataSheet4U.com
2Mb Ultra-Low Power Asynchronous CMOS SRAM
128K × 16bit
Overview
Features
The N02L63W3A is an integrated memory device
containing a 2 Mbit Static Random Access Memory
organized as 131,072 words by 16 bits. The device
is designed and fabricated using ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with a single chip
enable (CE) control and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently. The N02L63W3A is
optimal for various applications where low-power is
critical such as battery backup and hand-held
devices. The device can operate over a very wide
temperature range of -40oC to +85oC and is
available in JEDEC standard packages compatible
with other standard 128Kb x 16 SRAMs.
Product Family
• Single Wide Power Supply Range
2.3 to 3.6 Volts
• Very low standby current
2.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
• Simple memory control
Single Chip Enable (CE)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.8V
• Very fast output enable access time
30ns OE access time
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Part Number
N02L63W3AB
N02L63W3AT
N02L63W3AB2
N02L63W3AT2
Package Type
Operating
Temperature
Power
Supply
(Vcc)
Speed
Standby
Operating
Current (ISB), Current (Icc),
Typical
Typical
48 - BGA
44 - TSOP II
48 - BGA Green
-40oC to +85oC
2.3V - 3.6V
55ns @ 2.7V
70ns @ 2.3V
2 µA
2 mA @ 1MHz
44 - TSOP II Green
©2008 SCILLC. All rights reserved.
July 2008 - Rev. 15
Publication Order Number:
N02L63W3A/D

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N02L63W3A
Pin Configurations
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIN
ONE
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 VSS
33 VCC
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
123456
A LB OE A0 A1 A2 NC
B I/O8 UB A3 A4 CE I/O0
C I/O9 I/O10 A5 A6 I/O1 I/O2
D VSS I/O11 NC A7 I/O3 VCC
E VCC I/O12 NC A16 I/O4 VSS
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H NC A8 A9 A10 A11 NC
48 Pin BGA (top)
6 x 8 mm
Pin Descriptions
Pin Name
A0-A16
WE
CE
OE
LB
UB
I/O0-I/O15
NC
VCC
VSS
Pin Function
Address Inputs
Write Enable Input
Chip Enable Input
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
Not Connected
Power
Ground
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N02L63W3A
Functional Block Diagram
Address
Inputs
A0 - A3
Word
Address
Decode
Logic
Address
Inputs
A4 - A16
Page
Address
Decode
Logic
CE
WE
OE Control
UB Logic
LB
32K Page
x 16 word
x 16 bit
RAM Array
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Input/
Output
Mux
and
Buffers
I/O0 - I/O7
I/O8 - I/O15
Functional Description
CE WE OE UB LB
I/O0 - I/O151
MODE
POWER
HXXXX
L XXHH
L L X3 L1 L1
L H L L1 L1
L HHX X
High Z
High Z
Data In
Data Out
High Z
Standby2
Active
Write3
Read
Active
Standby
Active
Active
Active
Active
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item
Symbol
Test Condition
Input Capacitance
I/O Capacitance
CIN VIN = 0V, f = 1 MHz, TA = 25oC
CI/O VIN = 0V, f = 1 MHz, TA = 25oC
1. These parameters are verified in device characterization and are not 100% tested
Min Max Unit
8 pF
8 pF
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