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EN25F16
EN25F16
16 Megabit Serial Flash Memory with 4Kbytes Uniform Sector
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
16 Mbit Serial Flash
- 16 M-bit/2048 K-byte/8192 pages
- 256 bytes per programmable page
High performance
- 100MHz clock rate
Low power consumption
- 5 mA typical active current
- 1 μA typical power down current
Uniform Sector Architecture:
- 512 sectors of 4-Kbyte
- 32 blocks of 64-Kbyte
- Any sector or block can be
erased individually
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Page program time: 1.5ms typical
- Sector erase time: 150ms typical
- Block erase time 800ms typical
- Chip erase time: 18 Seconds typical
Lockable 512 byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- 16 pin SOP 300mil body width
- All Pb-free packages are RoHS compliant
Industrial temperature Range
GENERAL DESCRIPTION
The EN25F16 is a 16M-bit (2048K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25F16 is designed to allow either single Sector at a time or full chip erase operation. The
EN25F16 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2008/06/23

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Figure.1 CONNECTION DIAGRAMS
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EN25F16
8 - LEAD SOP / DIP
8 - CONTACT VDFN
16 - LEAD SOP
This Data Sheet may be revised by subsequent versions
2
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2008/06/23

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Figure 2. BLOCK DIAGRAM
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EN25F16
This Data Sheet may be revised by subsequent versions
3
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2008/06/23

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SIGNAL DESCRIPTION
EN25F16
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See
SPI Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device
is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the
devices power consumption will be at standby levels unless an internal erase, program or status
register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, CS# must transition from high to low before a new instruction will be
accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought
low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will
be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same
SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol
CLK
DI
DO
CS#
WP#
HOLD#
Vcc
Vss
Pin Name
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Enable
Write Protect
Hold Input
Supply Voltage (2.7-3.6V)
Ground
This Data Sheet may be revised by subsequent versions
4
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2008/06/23

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MEMORY ORGANIZATION
EN25F16
The memory is organized as:
z 2,097,152 bytes
z Uniform Sector Architecture
32 blocks of 64-Kbyte
512 sectors of 4-Kbyte
z 8192 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 2. Uniform Block Sector Architecture
Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Sector
511
496
495
480
479
464
463
448
447
432
431
416
415
400
399
384
383
368
367
352
351
336
335
320
319
304
303
288
287
272
271
256
1FF000
1F0000
1EF000
1E0000
1DF000
1D0000
1CF000
1C0000
1BF000
1B0000
1AF000
1A0000
19F000
190000
18F000
180000
17F000
170000
16F000
160000
15F000
150000
14F000
140000
13F000
130000
12F000
120000
11F000
110000
10F000
100000
Address range
1FFFFF
1F0FFF
1EFFFF
1E0FFF
1DFFFF
1D0FFF
1CFFFF
1C0FFF
1BFFFF
1B0FFF
1AFFFF
1A0FFF
19FFFF
190FFF
18FFFF
180FFF
17FFFF
170FFF
16FFFF
160FFF
15FFFF
150FFF
14FFFF
140FFF
13FFFF
130FFF
12FFFF
120FFF
11FFFF
110FFF
10FFFF
100FFF
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2008/06/23