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DATA SHEET
OKI
ASIC
www.DataSheet4U.com
PRODUCTS
MSM30R/32R/92R
0.5µm Sea Of Gates and
Customer Structured Arrays
August 2002

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CONTENTS
Description ................................................................................................................................................................1
Features ....................................................................................................................................................................1
MSM30R/32R/92R Family Listing .......................................................................................................................2
Array Architecture ...................................................................................................................................................3
MSM92R000 CSA Layout Methodology ........................................................................................................3
Electrical Characteristics .........................................................................................................................................5
Macro Library .........................................................................................................................................................10
Macrocells for Driving Clock Trees ..............................................................................................................11
Oki Advanced Design Center Cad Tools ..........................................................................................................1 2
Design Process .................................................................................................................................................13
Automatic Test Pattern Generation ..............................................................................................................14
Floorplanning Design Flow ...........................................................................................................................14
IEEE JTAG Boundary Scan Support .............................................................................................................15
Package Options .....................................................................................................................................................16
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MSM30R/32R/92R
Second-Generation 0.5µm Sea of Gates and Customer Structured Arrays
DESCRIPTION
Oki's second-generation 0.5µm ASIC products are available in both Sea Of Gates (SOG) and Customer
Structured Array (CSA) architectures. The MSM30R Series, MSM32R Series, and MSM92R Series all offer
increased density over their first-generation counterparts, as well as 3-V I/O buffers that are 5-V tolerant.
Both the SOG-based MSM30R Series and the CSA-based MSM92R Series use a three-layer metal process
on 0.5µm drawn (0.4µm L-effective) CMOS technology. The SOG-based MSM32R Series uses the same
SOG base-array architecture as the MSM30R Series, but offers two metal layers instead of three. The
semiconductor process is adapted from Oki's production-proven 16-Mbit DRAM manufacturing process.
The second-generation 0.5µm family retains the high speed and low power of Oki’s first-generation
0.5µm MSM13R/12R/98R family. The second-generation 0.5µm family also shares the same die sizes for
arrays with corresponding I/O counts, but the second-generation arrays can contain up to 60% more
gates than their first-generation counterparts. The second-generation family is optimized for 3-V core
operation, with optimized 3-V I/O buffers and 3-V I/O buffers that are 5-V tolerant, whereas the first-
generation family offers separate I/O buffers for mixed 3-V and 5-V operation. Oki's first-generation and
second-generation 0.5µm families together offer an unusually flexible mixed-voltage ASIC capability.
The 3-layer-metal MSM30R SOG Series contains 8 array bases, offering up to 448 I/O pads and over 600K
raw gates. The 2-layer metal MSM32R SOG Series contains five array bases, offering up to 320 I/O pads
and over 300K raw gates. These SOG array sizes are designed to fit the most popular Quad Flat Pack
(QFP) and Plastic Ball Grid Array (PBGA) packages. The MSM30R and MSM32R Series’ SOG architec-
ture allows rapid prototyping turnaround times, additionally offering the most cost-effective solution for
pad-limited circuits (particularly the 2-layer metal MSM32R Series).
The 3-layer-metal MSM92R CSA Series contains 36 array bases, offering a wider span of gate and I/O
counts than SOG Series. Oki uses the EPOCH memory compiler from Cascade Design Automation to
generate optimized single- and dual-port RAM macrocells for CSA designs. As such, the MSM92R Series
is suited to memory-intensive ASICs and high-volume designs where fine tuning of package size pro-
duces significant cost or real-estate savings.
FEATURES
• 0.5µm drawn two and three-layer metal CMOS
• Optimized 3.3-V core
• Optimized 3-V I/O and 3-V I/O that is 5-V tolerant
• SOG and CSA architecture availability
• 120-ps typical gate propagation delay (for a 2-input
4x-drive NAND gate with a fan-out of 2 and 0mm of
wire, operating at 3.3 V)
• Up to 1.2M raw gates and 624 pads
User-configurable I/O with VSS, VDD, TTL, 3-state,
and 1 mA ~ 24 mA options
• Slew-rate-controlled outputs for low-radiated noise
• Clock tree cells with 0.5-ns clock skew, worst-case
(fan-out 9000 at 75 MHz)
• User-configurable single and dual-port memories
• Specialized macrocells, including phase-locked loop,
GTL, PECL, and PCI cells
• Floorplanning for front-end simulation, back-end
layout controls, and link to synthesis
• JTAG boundary scan and scan-path ATPG
• Support for popular CAE systems, including
Cadence, IKOS, Mentor Graphics, Synopsys,
Viewlogic, and Zycad
Oki Semiconductor
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I MSM30R/32R/92R I ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
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MSM30R/32R/92R FAMILY LISTING
CSA Part#
MSM92RB01
MSM92RB02
MSM92RB03
MSM92RB04
MSM92RB05
MSM92RB06
MSM92RB07
MSM92RB08
MSM92RB09
MSM92RB10
MSM92RB11
MSM92RB12
MSM92RB13
MSM92RB14
MSM92RB15
MSM92RB16
MSM92RB17
MSM92RB18
MSM92RB19
MSM92RB20
MSM92RB21
MSM92RB22
MSM92RB23
MSM92RB24
MSM92RB25
MSM92RB26
MSM92RB27
MSM92RB28
MSM92RB29
MSM92RB30
MSM92RB31
MSM92RB32
MSM92RB33
MSM92RB34
MSM92RB35
MSM92RB36
CSA Master#
B92R020X020
B92R024X024
B92R026X026
B92R030X030
B92R032X032
B92R036X036
B92R038X038
B92R040X040
B92R042X042
B92R044X044
B92R048X048
B92R050X050
B92R052X052
B92R056X056
B92R060X060
B92R064X064
B92R068X068
B92R072X072
B92R076X076
B92R080X080
B92R084X084
B92R088X088
B92R092X092
B92R096X096
B92R100X100
B92R104X104
B92R108X108
B92R112X112
B92R118X118
B92R122X122
B92R126X126
B92R132X132
B92R138X138
B92R144X144
B92R150X150
B92R156X156
SOG Part#
MSM30R0020
MSM32R0050
MSM30R0050
MSM32R0080
MSM30R0080
MSM32R0120
MSM30R0120
MSM32R0190
MSM30R0190
MSM32R0300
MSM30R0300
MSM30R0440
I/O Pads
80
96
104
120
128
144
144
152
160
168
176
176
192
200
208
208
224
240
256
256
272
288
304
320
320
336
352
368
384
400
416
432
448
472
488
504
528
552
576
600
624
Raw Gates
14,688
22,784
27,440
37,720
43,296
56,000
56,000
63,176
70,336
78,352
86,304
86,304
103,904
114,400
123,968
123,968
144,900
167,464
191,660
191,660
217,488
244,948
274,040
306,072
306,072
338,496
372,552
408,240
445,560
484,512
525,096
569,096
613,012
682,644
730,664
780,316
857,072
941,360
1,025,488
1,115,000
1,206,400
Rows [1]
72
89
98
115
123
140
140
149
157
166
174
174
191
200
208
208
225
242
259
259
276
293
310
327
327
344
361
378
395
412
429
446
463
489
506
523
548
574
599
625
650
Columns
204
256
280
328
352
400
400
424
448
472
496
496
544
572
596
596
644
692
740
740
788
836
884
936
936
984
1032
1080
1128
1176
1224
1276
1324
1396
1444
1492
1564
1640
1712
1784
1856
Usable Gates [2]
11,750
18,227
21,952
30,176
34,637
26,880
42,000
47,382
52,752
58,764
38,837
60,413
72,733
80,080
49,587
86,778
101,430
117,225
72,831
126,496
143,542
161,666
180,866
110,186
195,886
216,637
238,433
261,274
276,247
300,397
325,560
352,840
367,807
409,586
438,398
468,190
514,243
564,816
615,293
669,000
723,840
1. Row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array.
2. Usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan,
RAM/ROM blocks, etc.
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ARRAY ARCHITECTURE
The primary components of a 0.5µm MSM30R/32R/92R circuit include:
• I/O base cells
• Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant)
• VDD and VSS pads dedicated to wafer probing
• Separate power bus for output buffers
• Separate power bus for internal core logic and input buffers
• Core base cells containing N-channel and P-channel pairs, arranged in column of gates
• Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC)
and output drive transistors (VDDO and VSSO).
Configurable I/O pads
for VDD, VSS, or I/O
I/O base cells
Separate power bus (VDDC, VSSC) for
internal core logic (2nd metal/3rd metal
1,2, or 3 layer metal
interconnection in
core area
Core base cell
with 4 transistors
VDD, VSS pads (4) in each
corner for
wafer probing only
Separate power bus (VDDO, VSSO)
over I/O cell for output buffers(2nd
metal/3rd metal)
Figure 7. MSM30R0000 Array Architecture
MSM92R000 CSA Layout Methodology
The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
- Identify the macrocell functions required and the minimum array size to hold the macrocell
functions.
Oki Semiconductor
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