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® Preliminary Data Book
FEATURES
s IBM®_VGA hardware-compatible
s Integrated RAMDAC
s Integrated programmable frequency synthesizer
— 65 MHz at 5.0V; 40 MHz at 3.3V
s Supports single 256K x 16 DRAM configuration
— Symmetric or asymmetric RAS/CAS-address DRAM
s Color STN panel support (CL-GD6225/’6235 only)
— Dual-scan color STN panel support (CL-GD6235 only)
— 8- and 16-bit interfaces (no extra components required)
— Up to 256 simultaneous colors from a palette of 256K
s Integrates color TFT panel support
— Supports 9-, 12-, 15-, and 18-bit TFT panels
— Up to 256 simultaneous colors from a palette of 256K
s Connects directly to local bus, ISA bus (PC AT) or PI
bus (CL-GD6205 connects to ISA bus only)
s Windows performance-improvement features
— True packed-pixel addressing
— Improved data latches for block moves
— Color expansion for 8 bits-per-pixel graphics
— 32 x 32 hardware cursor (2 bits-per-pixel)
s Supports 3.3V and 5.0V mixed-voltage operation
s Standby and Suspend modes save power
— Internal timers for backlight control and Standby mode
— Dedicated Hardware-suspend Mode pin
— 32-kHz DRAM refresh clock in Suspend mode
s Frame-Accelerator for low-active power
— No additional DRAMs required
— Supports self-refresh DRAMs
s Simultaneous CRT and LCD (SimulSCAN) operation
(cont.)
Single DRAM LCD/VGA
Controllers for Monochrome/
Color Notebook Computers
OVERVIEW
The CL-GD62XX (CL-GD6205/’6215/’6225/’6235) fam-
ily of advanced single-chip flat panel VGA controllers are
designed for use in portable systems with stringent
power consumption and form-factor requirements.
Product family pin compatibility provides easy upgrade
capability to color or higher-performance systems.
Integration of the frequency synthesizer, RAMDAC,
monochrome and color STN/TFT panel interfaces mini-
mizes the form-factor requirement for color and mono-
chrome graphics subsystems. All necessary panel-
power sequencing logic has been integrated into the
CL-GD62XX family, and a complete graphics subsystem
can be built using only two active components (in less
than three square inches).
The CL-GD62XX family uses a single 256K x 16 DRAM
(or four 256K x 4 DRAMs) for video memory. For added
flexibility, dual-CAS*-DRAM and dual-WE*-DRAM con-
figurations are supported.
With integrated Frame-Accelerator technology, the
CL-GD62XX controllers feature low-power LCD opera-
tion, yet support high LCD panel vertical-refresh rates.
No additional DRAMs are required for frame
(cont.)
Functional
Block Diagram
3.3V
3.3V or 5V
256K x 16
DRAM
3.3V or 5V
CL-GD62XX
160-Pin PQFP
3.3V
or
5V
3.3V
or
5V
5
4
3
2
1
0
ANALOG CRT
5
4
3
2
1
0
REFERENCE FREQUENCY
MONOCHROME OR
COLOR LCD PANEL
October 1993
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CL-GD62XXw w w . D a t a S h e e t 4 U . c o
LCD VGA Controller Family
FEATURES (cont.)
s 64-shade grayscale at 640 x 480 resolution on mono-
chrome STN LCD
s CRT Resolution up to 1024 x 768 with 16 colors
s CRT Resolution up to 800 x 600 with 256 colors
s 132-column text modes on CRTs
s Automatic vertical expansion or centering option for
LCD panels
s 160-pin (EIAJ standard) PQFP package
OVERVIEW (cont.)
acceleration because the CL-GD62XX family efficiently
uses the unused portions of video memory.
Since the CL-GD62XX can use a 3.3V or 5.0V power
supply, mixed-voltage operation is optimized for quick
implementation of a notebook computer with reduced
power consumption. The video memory, host bus inter-
face, panel interface, and CRT interface each may be
implemented with either 3.3V or 5.0V used in any com-
bination.
The CL-GD62XX family also offers flexibility in host-
interface connections. In addition to an ISA-bus connec-
tion, the CL-GD6215/’25/’35 can be connected directly
to a PI- or local-bus to provide additional graphics perfor-
mance. The 16-bit local-bus interface can be used
directly with ’386SX microprocessors. Connections to
32-bit buses, such as ’386DX or ’486 microprocessors,
can be made by using the 16-bit modes or with a mini-
mum of extra components. The CL-GD62XX controllers
also use the ’486 Burst mode for multiple-cycle
accesses.
The CL-GD62XX family offers true packed-pixel
addressing, color expansion for 8-bit-per-pixel graphics,
and hardware cursor, thus improving Windows perfor-
mance. Other incorporated features, such as memory
write buffers and internal asynchronous display data
FIFOs, also boost performance.
Standby and Suspend power-management modes
reduce power consumption when the system is not in
active use. The internal Standby Counter initiates
Standby mode without software intervention. During this
reduced-power mode, the LCD panel is turned off while
the video memory can be accessed and modified. In
Suspend mode, all I/O pins, except a dedicated Sus-
pend Mode pin, are deactivated to further reduce power
consumption. In this mode, the video memory data is
preserved, but cannot be accessed; this is useful in sit-
uations when a system remains inactive for a relatively
long period of time.
The CL-GD62XX family also features SimulSCAN, a
technique introduced by Cirrus Logic for achieving
simultaneous CRT and LCD operation. SimulSCAN
allows portable computers to become a key part of pre-
sentation environments for sales-force automation, field
service, and educational organizations. SimulSCAN is
supported in both single- and dual-scan, color and
monochrome, LCD panels, and fixed- and multi-fre-
quency analog CRTs.
Proprietary algorithms in the CL-GD62XX family
expand the available palette depth for color flat panels.
High clock rates provide extended-resolution capability
in CRT mode. At 1024 x 768 resolution, 16 simulta-
neous colors can be displayed; at 640 x 480 resolution,
up to 256 simultaneous colors are available.
The CL-GD62XX family offers highly integrated, pin-
compatible LCD VGA controllers that provide
unmatched performance while featuring design flexibil-
ity in CPU, video-memory interface, and power man-
agement. The CL-GD62XX family can also drive a wide
variety of color and monochrome LCD flat-panel dis-
plays.
Controller Selection Guide
CL-GD62XX
Device
CL-GD6205
CL-GD6215
CL-GD6225
CL-GD6235
Buses Supported
ISA PI Local Mono. STN
Panels Supported
Color TFT Color STN Dual-Scan Color STN
2 October 1993
PRELIMINARY DATA BOOK

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LCD VGA Controller Family
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Table of Contents — PAGE #s INCORRECT; USE BOOKMARKS
1. PIN INFORMATION ............................... 7
1.1 Pin Diagram for the CL-GD6205.......................... 7
1.2 Pin Diagram for the CL-GD6215.......................... 8
1.3 Pin Diagram for the CL-GD6225 and
CL-GD6235. ......................................................... 9
1.4 Typical Dual Monochrome Panel Connections —
ISA Bus Using 256K x 16 DRAM
with Dual CAS*................................................... 10
1.5 STN Color Panel Connections — ’386SL/’486SL
PI Bus Using 256K x 4 DRAMs ......................... 11
1.6 TFT Color Panel Connections — ’386SX
Local Bus Using 256K x 16 DRAM
with Dual WE* .................................................... 12
1.7 TFT Color Panel Connections — ’386DX
Local Bus Using 256K x 16 DRAMs
with Dual WE* .................................................... 13
1.8 Dual-Scan STN Color Panel — ’486DX Local
Bus/256K x 16 DRAM with Dual CAS*.............. 14
1.9 Pin Summary...................................................... 15
2. DETAILED PIN DESCRIPTIONS ........ 21
2.1 Host Interface — ISA Bus Mode ........................ 21
2.2 Host Interface — ’386SL/’486SL (PI Bus Mode)
(CL-GD6215/’25/’35 only) .................................. 25
2.3 Host Interface — Local Bus
(CL-GD6215/’25/’35 only) .................................. 27
2.4 Dual-Frequency Synthesizer Interface .............. 31
2.5 CRT Interface ..................................................... 32
2.6 Display Memory Interface .................................. 34
2.7 Miscellaneous Pins ............................................ 36
2.8 Power Management Pins................................... 38
2.9 LCD Flat Panel Interface.................................... 40
2.10 Power And Ground Pins .................................... 42
3. FUNCTIONAL DESCRIPTION............ 45
3.1 General............................................................... 45
3.2 Functional Blocks ............................................... 45
3.2.1 CPU Interface ................................................. 45
3.2.2 CPU Write Buffer ............................................ 45
3.2.3 Graphics Controller......................................... 45
3.2.4 Memory Arbitrator ........................................... 45
3.2.5 Memory Sequencer ........................................ 45
3.2.6 CRT Controller ................................................ 45
3.2.7 LCD Flat-Panel Controller .............................. 45
3.2.8 Video FIFO...................................................... 45
3.2.9 Attribute Controller.......................................... 45
3.2.10 Palette DAC .................................................... 46
3.2.11 Dual-Frequency Synthesizer .......................... 46
3.3 Functional Operation.......................................... 46
3.3.1 CPU Access to Registers............................... 46
3.3.2 CPU Access to Display Memory .................... 46
3.3.3 Display Memory Refresh................................ 46
3.3.4 Screen Refresh .............................................. 46
3.4 Performance ...................................................... 46
3.5 Compatibility ...................................................... 46
3.6 Data Bus Interface for 32-Bit Processors.......... 46
3.6.1 486 Burst Mode Support ............................... 47
3.6.2 CL-GD62XX Address Decode and
Latching .......................................................... 47
3.6.3 Bus Cycle Restart .......................................... 47
3.6.4 Other Considerations ..................................... 47
3.7 LCD Flat Panel Interface ................................... 48
3.8 Intelligent Power Management and
Sequencing........................................................ 49
3.8.1 Normal Mode.................................................. 49
3.8.2 Hardware Power-Management Modes.......... 49
3.8.3 Standby Mode ................................................ 49
3.8.3.1 Initiating/Entering Standby Mode................ 50
3.8.3.2 Terminating/Exiting Standby Mode ............. 50
3.8.4 Suspend Mode ............................................... 50
3.8.4.1 Hardware-Suspend Mode........................... 50
3.8.4.2 Software-Suspend Mode ............................ 51
3.8.4.3 Initiating/Entering Suspend Mode............... 51
3.8.4.4 Terminating/Exiting Suspend Mode............ 51
3.8.5 Power Sequencing ......................................... 51
3.8.5.1 LCD Panel Power-Down Sequence ........... 51
3.8.5.2 LCD Panel Power-Up Sequence................ 51
3.8.6 Additional Power Management
Features ......................................................... 52
3.8.6.1 LCD-only Operation
(CRT Disable) ............................................. 52
3.8.6.2 CRT-only Operation
(LCD Panel Disable) ................................... 52
3.8.6.3 Backlight Timer ........................................... 52
3.8.6.4 ACTi Function ............................................. 52
3.9 Internal RAMDAC.......................................... 52
3.9.1 RAMDACVideo Operation.......................... 53
3.9.2 Analog Outputs............................................... 53
3.9.3 Writing to the Color Look-up Table................. 53
3.9.4 Reading from the Color Look-up Table .......... 53
4. CL-GD62XX VIDEO
MODE TABLES ....................................55
4.1 CRT Video Modes ............................................ 55
4.2 LCD Flat Panel Video Modes ........................... 57
October 1993
PRELIMINARY DATA BOOK
TABLE OF CONTENTS
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LCD VGA Controller Family
Table of Contents (cont.)
5. VGA REGISTER PORT MAP .............. 59
6. REGISTER INFORMATION................. 61
6.1 CL-GD62XX Extended-Register Details ............65
6.1.1 SR6: Unlock All CL-GD62XX Register
Extensions.......................................................65
6.1.2 SR7: Extended Sequencer Modes .................66
6.1.3 SR8: Miscellaneous Control............................67
6.1.4 SR9, SRA, SR14, SR15, SR19: Scratch-Pad
Registers 0-4...................................................69
6.1.5 SRB, SRC, SRD, SRE: VCLK0, 1, 2, 3
Numerator Value .............................................70
6.1.6 SRF: DRAM Control........................................71
6.1.7 SR10, 30, 50, 70, 90, B0, D0, F0: Graphics
Cursor X Position ............................................73
6.1.8 SR11, 31, 51, 71, 91, B1, D1, F1: Graphics
Cursor Y Position ............................................74
6.1.9 SR12: Graphics Cursor Attributes...................75
6.1.10 SR13: Graphics Cursor Pattern
Address Offset.................................................76
6.1.11 SR16: Miscellaneous Control 2 ......................77
6.1.12 SR1A: Dual-Scan Color Control
(CL-GD6235 only) ...........................................78
6.1.13 SR1B, SR1C, SR1D, SR1E: VCLK0, 1, 2, 3
Denominator and Post Scalar Value...............79
6.1.14 SR1F: Memory Clock Frequency
Programming...................................................80
6.1.15 STAT: Input Status Register 1 .........................81
6.1.16 GR0: Set/Reset Register (CL-GD62XX
Extensions)......................................................82
6.1.17 GR1: Enable Set/Reset Register
(CL-GD62XX Extensions) ...............................83
6.1.18 GR5: Mode Register
(CL-GD62XX Extensions) ...............................84
6.1.19 GR9: Offset Register 0....................................85
6.1.20 GRA: Offset Register 1 ...................................86
6.1.21 GRB: Graphics Controller
Mode Extensions.............................................87
6.1.22 CR19: Interlace End........................................88
6.1.23 CR1A: Interlace Control ..................................89
6.1.24 CR1B: Extended Display Controls..................90
6.1.25 CR1C: Flat-Panel Interface.............................92
6.1.26 CR1D: Flat-Panel Display Controls ................94
6.1.27 CR1E: Flat-Panel Shading..............................96
6.1.28 CR1F: Flat Panel Modulation Control .............98
6.1.29 CR20: Power Management Register..............99
6.1.30 CR21: Power-Down Timer Control ...............101
6.1.31 CR23: Suspend Mode Input Switch Debounce
Timer ............................................................. 102
6.1.32 CR25: CL-GD62XX Part Status
Register......................................................... 103
6.1.33 CR27: CL-GD62XX Part ID Register ........... 104
6.1.34 CR29: CL-GD62XX Configuration
Register......................................................... 105
6.1.35 R0X: LCD Timing Register — Horizontal Total for
80-Column and Mode 13h............................ 106
6.1.36 R1X: LCD Timing Register — Horizontal Total
Enable and 40-Column Horizontal Total....... 107
6.1.37 R2X: LCD Timing — LFS Vertical Counter Value
Compare (3C2[7:6] = ‘11’) ............................ 108
6.1.38 R3X: LCD Timing — LFS Vertical Counter Value
Compare (3C2[7:6] = ‘10’) ............................ 109
6.1.39 R4X: LCD Timing — LFS Vertical Counter Value
Compare (3C2[7:6] = ‘01’) ............................ 110
6.1.40 R5X: LCD Timing — LFS Vertical Counter Value
Compare (3C2[7:6] = ‘00’) .............................111
6.1.41 R6X: LCD Timing — Overflow (Most-Significant)
Bits for LFS Signal Compare........................ 112
6.1.42 R7X: LCD Timing — Panel Signal Control for
Color TFT Panels.......................................... 113
6.1.43 R8X: LCD Timing — STN Color Panel Data
Format........................................................... 114
6.1.44 R9X: LCD Timing — TFT Panel
Data Format.................................................. 115
6.1.45 RAX: LCD Timing — TFT Panel HSYNC Position
Control .......................................................... 116
6.1.46 RBX: LCD Timing — Special Functions for
CL-GD6235 Only .......................................... 117
6.2 132-Column Alphanumeric Mode .................... 118
6.2.1 Write Buffer and Display FIFO...................... 118
6.3 Hardware Cursor.............................................. 118
6.4 Graphics Hardware Cursor .............................. 120
7. ELECTRICAL SPECIFICATIONS ..... 121
7.1 Absolute Maximum Ratings ............................. 121
7.2 DC Specifications (Digital) .............................. 122
7.3 DC Specifications (Palette DAC) ..................... 123
7.4 DC Specifications
(Frequency Synthesizer).................................. 124
7.5 DAC Characteristics......................................... 124
7.6 List of Waveforms ............................................ 125
8. PACKAGE DIMENSIONS ................. 149
9. ORDERING INFORMATION ............. 150
9.1 Package Marking Numbering Guide................ 150
4
TABLE OF CONTENTS
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PRELIMINARY DATA BOOK

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LCD VGA Controller Family
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List of Figures
Figure 2–1.
Figure 2–2.
Figure 7–1.
Figure 7–2.
Figure 7–3.
Figure 7–4.
Figure 7–5.
Figure 7–6.
Figure 7–7.
Figure 7–8.
Figure 7–9.
Typical Memory Clock Filter . . . . . . . . 35
Typical Video Clock Filter . . . . . . . . . . 35
Bus Signal Timing (ISA Bus) . . . . . . . 131
BALE Timing (ISA Bus) . . . . . . . . . . . 132
EROM* Timing (ISA Bus) . . . . . . . . . 133
AEN Timing (ISA Bus). . . . . . . . . . . . 133
PI Bus Interface Timing. . . . . . . . . . . 135
CLK1X, CLK2X Timing
(Local Bus) . . . . . . . . . . . . . . . . . . . . 136
Reset Timing (Local Bus) . . . . . . . . . 137
ADS#, LBA# Timing (Local Bus)
(Not Pipelined) . . . . . . . . . . . . . . . . . 138
LBA#, BS16# Timing (Local Bus)
(Pipelined). . . . . . . . . . . . . . . . . . . . . 139
Figure 7–10. BRDY# Delay (Local Bus). . . . . . . . .140
Figure 7–11. Read Data Timing (Local Bus) . . . . .140
Figure 7–12. Buffer Control Timing: 16-Bit Cycle
(’486 Local Bus) . . . . . . . . . . . . . . . .141
Figure 7–13. Display-Memory Bus Read Timing
(t = MCLK) . . . . . . . . . . . . . . . . . . . .143
Figure 7–14. Display-Memory Bus Write Timing . .145
Figure 7–15. CAS*-Before-RAS* Refresh Timing
(Display Memory Bus). . . . . . . . . . . .146
Figure 7–16. Reset Timing . . . . . . . . . . . . . . . . . . .147
Figure 7–17. STN Monochrome and Color-Passive
LCD Interface Timing . . . . . . . . . . . .149
Figure 7–18. TFT, EL , Plasma Color, and
Monochrome Single-Scan LCD Interface
Timing . . . . . . . . . . . . . . . . . . . . . . . .151
List of Tables
Table 1–1.
Table 1–2.
Table 1–3.
Table 1–4.
Table 1–5.
Table 1–6.
Table 1–7.
Table 1–8.
Table 4–1.
Table 4–2.
Table 4–3.
Table 4–4.
Table 5–1.
Table 6–1.
Table 6–2.
Table 6–3.
Table 7–0.
Table 7–1.
Table 7–2.
Table 7–3.
Host Interface . . . . . . . . . . . . . . . . . . . 19
CRT Interface . . . . . . . . . . . . . . . . . . . 20
LCD Flat Panel Interface. . . . . . . . . . . 20
Display Memory Interface . . . . . . . . . . 21
Power Management Pins . . . . . . . . . . 22
Synchronizer/Clock Interface . . . . . . . 22
Miscellaneous Pins . . . . . . . . . . . . . . . 22
Power and Ground . . . . . . . . . . . . . . . 23
IBM® Standard VGA Video
Modes . . . . . . . . . . . . . . . . . . . . . . . . . 59
Cirrus Logic Extended CRT Video
Modesa . . . . . . . . . . . . . . . . . . . . . . . . 60
IBM Standard VGA Video Modes . . . . 61
Cirrus Logic Extended LCD Video
Modea . . . . . . . . . . . . . . . . . . . . . . . . . 61
VGA Register Port Map. . . . . . . . . . . . 63
512K-Byte Memory with 4K-Byte
Granularity and VGA Mapping . . . . . . 89
Typical Power-Down Timer
Settings . . . . . . . . . . . . . . . . . . . . . . . 105
Programming the Graphics Hardware
Cursor . . . . . . . . . . . . . . . . . . . . . . . . 124
Output Loading Values Table . . . . . . 127
Bus Signal Timing (ISA Bus) . . . . . . . 130
BALE Timing (ISA Bus) . . . . . . . . . . . 132
EROM* Timing (ISA Bus) . . . . . . . . . 133
Table 7–4.
Table 7–5.
Table 7–6.
Table 7–7.
Table 7–8.
Table 7–9.
Table 7–10.
Table 7–11.
Table 7–12.
Table 7–13.
Table 7–14.
Table 7–15.
Table 7–16.
Table 7–17.
Table 7–18.
Table 7–19.
AEN Timing (ISA Bus). . . . . . . . . . . .133
PI Bus-Interface Timing. . . . . . . . . . .134
CLK1X, CLK2X Timing
(Local Bus) . . . . . . . . . . . . . . . . . . . .136
Reset Timing (Local Bus) . . . . . . . . .137
ADS#, LBA# Timing (Local Bus)
(Not Pipelined) . . . . . . . . . . . . . . . . .138
LBA#, BS16# Timing (Local Bus)
(Pipelined). . . . . . . . . . . . . . . . . . . . .139
BRDY# Delay (Local Bus). . . . . . . . .140
Read Data Timing (Local Bus) . . . . .140
Buffer Control Timing: 16-Bit Cycle
(’486 Local Bus) . . . . . . . . . . . . . . . .141
Display-Memory Bus Read Timing
(tb = MCLK) . . . . . . . . . . . . . . . . . . .142
Display-Memory Bus Write Timing
(tb = MCLK) . . . . . . . . . . . . . . . . . . .144
CAS*-Before-RAS* Refresh Timing
(Display Memory Bus). . . . . . . . . . . .146
Reset Timing . . . . . . . . . . . . . . . . . . .147
STN Monochrome and Color-Passive
LCD Interface Timing . . . . . . . . . . . .148
TFT Color Single-Scan LCD Interface
Timing, . . . . . . . . . . . . . . . . . . . . . . .150
Frequency Synthesizer Input Clock
Specification . . . . . . . . . . . . . . . . . . .152
October 1993
PRELIMINARY DATA BOOK
5