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Multi-Output Controller with Integrated MOSFET
Drivers for AMD SVI Capable Mobile CPUs
ISL6265C
The ISL6265C is a multi-output controller with embedded
gate drivers. A single-phase controller powers the
Northbridge (VDDNB) portion of the CPU. The two
remaining controller channels can be configured for
two-phase or individual single-phase outputs. For
uniplane CPU applications, the ISL6265C is configured as
a two-phase buck converter. This allows the controller to
interleave channels to effectively double the output
voltage ripple frequency, and thereby reduce output
voltage ripple amplitude with fewer components, lower
component cost, reduced power dissipation, and smaller
area. For dual-plane processors, the ISL6265C can be
configured as independent single-phase controllers
powering VDD0 and VDD1.
The heart of the ISL6265C is the patented R3
Technology™, Intersil’s Robust Ripple Regulator
modulator. Compared with the traditional buck regulator,
the R3 Technologyhas a faster transient response. This
is due to the R3 modulator commanding variable
switching frequency during a load transient.
The Serial VID Interface (SVI) allows dynamic
adjustment of the Core and Northbridge output voltages
independently and in combination from 0.500V to 1.55V.
Core and Northbridge output voltages achieve a 0.5%
system accuracy over-temperature.
A unity-gain differential amplifier is provided for remote
CPU die sensing. This allows the voltage on the CPU die
to be accurately regulated per AMD mobile CPU
specifications. Core output current sensing is realized
using lossless inductor DCR sensing. All outputs feature
overcurrent, overvoltage and undervoltage protection.
Features
• Core Configuration Flexibility
- Dual Plane, Single-Phase Controllers
- Uniplane, Two-Phase Controller
• Precision Voltage Regulators
- 0.5% System Accuracy Over-temperature
• Voltage Positioning with Adjustable Load Line and Offset
• Internal Gate Drivers with 2A Driving Capability
• Differential Remote CPU Die Voltage Sensing
• Core Differential Current Sensing: DCR or Resistor
• Northbridge Lossless rDS(ON) Current Sensing
• Serial VID Interface
- Two Wire Clock and Data Bus
- Supports High-Speed I2C
- 0.500V to 1.55V in 12.5mV Steps
- Supports PSI_L Power-Saving Mode
• Core Outputs Feature Phase Shedding with PSI_L
• Adjustable Output-Voltage Offset
• Digital Soft-Start of all Outputs
• User Programmable Switching Frequency
• Static and Dynamic Current Sharing (Uniplane Core)
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free (RoHS compliant)
Applications*(see page 26)
• AMD Griffin Platform CPU
• Notebook Core/GPU Voltage Regulators
Related Literature*(see page 26)
• See FN6884 for “Multi-Output Controller with Integrated
MOSFET Drivers for AMD SVI Capable Mobile CPUs”
Simplified System Diagram
POWER
STAGE
CORE_0
ISL6265C
POWER
STAGE
CORE_1
POWER
STAGE
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1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL6265C
Functional Block Diagram
SVC
SVD
PWROK
OFS/FIXEN
RTN_NB VSEN_NB
FB_NB
COMP_NB FSET_NB
VNB
IFSET_NB
PVCC
1 3.0kΩ
1.5kΩ
NO DROOP
PSI_L
I_OFS
VREF_NB
VREF0
VREF1
E/A
VREF_NB
FLT
MODULATOR
NB
VIN
MOSFET
DRIVER
SHOOT-THRU
PROTECTION
DE MODE
PSI_L
OCSET_NB
OCSET
RBIAS
VW0
COMP0
FB0
VDIFF0
VSEN0
RTN0
ISP0
ISN0
ISP1
ISN1
VSEN1
RTN1
VDIFF1
FAULT
PROTECTION
FLT
VNB
V0 RTN1
V1
ISEN0
ISEN1
POWER-ON
RESET AND
SOFT-START
LOGIC
MODE
IVW0
PVCC
I_OFS
V0
1
NO
DROOP
CURRENT
SENSE
MODE
E/A
VREF0
VIN
ISEN0
MODE
ISEN1
CURRENT
BALANCE
CURRENT
SENSE
NO
DROOP
V1
1
VREF1
MODE
I_OFS
E/A
FLT
MOSFET
DRIVER
SHOOT-THRU
PROTECTION
DE MODE
MODULATOR
CORE
PSI_L
PVCC
FLT
MOSFET
DRIVER
SHOOT-THRU
PROTECTION
DE MODE
IVW1
PSI_L
FB1
COMP1 VW1
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6265C
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PGND_NB
PVCC
VCC
ENABLE
PGOOD
GND
VIN
BOOT0
UGATE0
PHASE0
LGATE0
PGND0
BOOT1
UGATE1
PHASE1
LGATE1
PGND1
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ISL6265C
Ordering Information
PART NUMBER (Note)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL6265CHRTZ
6265C HRTZ
-10 to +100
48 Ld 6x6 TQFN
L48.6x6
ISL6265CHRTZ-T
6265C HRTZ
-10 to +100
48 Ld 6x6 TQFN
Tape and Reel
L48.6x6
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6265C. For more information on MSL please
see techbrief TB363.
Pin Configuration
ISL6265C
(48 LD TQFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
OFS/VFIXEN 1
PGOOD 2
PWROK 3
SVD 4
SVC 5
ENABLE 6
RBIAS 7
OCSET 8
VDIFF0 9
FB0 10
COMP0 11
VW0 12
49
GND
[BOTTOM]
36 BOOT_NB
35 BOOT0
34 UGATE0
33 PHASE0
32 PGND0
31 LGATE0
30 PVCC
29 LGATE1
28 PGND1
27 PHASE1
26 UGATE1
25 BOOT1
13 14 15 16 17 18 19 20 21 22 23 24
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ISL6265C
Pin Descriptions
PIN(s)
1
2
3
4
5
6
7
8
9, 19
10, 20
11, 21
12, 22
13, 14, 23, 24
15, 16
18, 17
30
31, 29
32, 28
33, 27
SYMBOL(s)
OFS/VFIXEN
PGOOD
PWROK
SVD
SVC
ENABLE
RBIAS
OCSET
VDIFF0, VDIFF1
FB0, FB1
COMP0, COMP1
VW0, VW1
ISP0, ISN0, ISP1,
ISN1
VSEN0, RTN0
VSEN1, RTN1
PVCC
LGATE0, LGATE1
PGND0, PGND1
PHASE0, PHASE1
DESCRIPTION
A resistor from this pin to GND programs a DC current source, which generates a positive
offset voltage across the resistor between FB and VDIFF pins. In this case, the OFS pin
voltage is +1.2V and VFIX mode is not enabled. If OFS is pulled up to +3.3V, VFIX mode
is enabled, the DAC decodes the SVC and SVD inputs to determine the programmed
voltage, and the OFS function is disabled. If OFS is pulled up to +5V, the OFS function
and VFIX mode are disabled.
Controller power-good open-drain output. This pin is typically pulled up externally by a
2.0kΩ resistor to +3.3V. During normal operation, this pin indicates whether all output
voltages are within specified overvoltage and undervoltage limits and no overcurrent
condition is present. If any output voltage exceeds these limits or a reset event occurs,
the pin is pulled low. This pin is always low prior to the end of soft-start.
System power good input. When this pin is high, the SVI interface is active and I2C
protocol is running. While this pin is low, the SVC, SVD, and VFIXEN input states
determine the pre-PWROK metal VID or VFIX mode voltage. This pin must be low prior
to the ISL6265C PGOOD output going high per the AMD SVI Controller Guidelines.
This pin is the serial VID data bidirectional signal to and from the master device on the
AMD processor.
This pin is the serial VID clock input from the AMD processor.
Digital input enable. A high level logic signal on this pin enables the ISL6265C.
A 117kΩ resistor from RBIAS to GND sets internal reference currents. The addition of
capacitance to this pin must be avoided and can create instabilities in operation.
CORE_0 and CORE_1 common overcurrent protection selection input. The voltage on this
pin sets the (ISPx - ISNx) voltage limit for OC trip.
Output of the CORE_0 and CORE_1 differential amplifiers.
These pins are the output voltage feedback to the inverting input of the CORE_0 and
CORE_1 error amplifiers.
The output of the CORE_0 and CORE_1 controller error amplifiers respectively. FBx,
VDIFFx, and COMPx pins are tied together through external R-C networks to compensate
the regulator
A resistor from this pin to corresponding COMPx pin programs the switching frequency
(for example, 6.81k ~ 300kHz).
These pins are used for differentially sensing the corresponding channel output current.
The sensed current is used for channel balancing, protection, and core load line
regulation.
Connect ISN0 and ISN1 to the node between the RC sense elements surrounding the
inductor of their respective channel. Tie the ISP0 and ISP1 pins to the VCORE side of
their corresponding channel’s sense capacitor. These pins can also be used for discrete
resistor sensing.
Inputs to the CORE_0 VR controller precision differential remote sense amplifier. Connect
to the sense pins of the VDD0_FB[H,L] portion of the processor.
Inputs to the CORE_1 VR controller precision differential remote sense amplifier. Connect
to the sense pins of the VDD1_FB[H,L] portion of the processor. The RTN1 pin is also
used for detection of the VDD_PLANE_STRAP signal prior to enable.
The power supply pin for the internal MOSFET gate drivers of the ISL6265C. Connect this
pin to a +5V power supply. Decouple this pin with a quality 1.0µF ceramic capacitor.
Connect these pins to the corresponding lower MOSFET gate(s).
The return path of the lower gate driver for CORE_0 and CORE_1 respectively. Connect
these pins to the corresponding sources of the lower MOSFETs.
Switch node of the CORE_0 and CORE_1 controllers. Connect these pins to the sources
of the corresponding upper MOSFET(s). These pins are the return path for the upper
MOSFET drives.
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ISL6265C
Pin Descriptions (Continued)
PIN(s)
34, 26
SYMBOL(s)
UGATE0, UGATE1
DESCRIPTION
Connect these pins to the corresponding upper MOSFET gate(s). These pins control the
upper MOSFET gate(s) and are monitored for shoot-through prevention.
35, 25
BOOT0, BOOT1
These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect
these pins to appropriately chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC pin provide the necessary bootstrap charge.
36
BOOT_NB
This pin is the upper gate drive supply voltage for the Northbridge controller. Connect an
appropriately sized ceramic bootstrap capacitor between the BOOT_NB and PHASE_NB
pins. An internal bootstrap diode connected to the PVCC pin provides the necessary
bootstrap charge.
37
UGATE_NB
Upper MOSFET gate signal from Northbridge controller.
38
PHASE_NB
Switch node of the Northbridge controller. This pin should connect to the source of the
Northbridge channel upper MOSFET(s).
39
LGATE_NB
Lower MOSFET gate signal from Northbridge controller.
40
PGND_NB
The return path of the Northbridge controller lower gate driver. Connect this pin to the
source of the lower MOSFET(s).
41
OCSET_NB
Overcurrent protection selection input for the Northbridge controller. A resistor from this
pin to PHASE_NB sets the OC trip point.
43, 42
VSEN_NB, RTN_NB Remote Northbridge voltage sense input and return. Connect isolated traces from these
pins to the Northbridge sense points of the processor.
44
FSET_NB
A resistor from this pin to GND programs the switching frequency of the Northbridge
controller (for example, 22.1k ~ 260kHz).
45
COMP_NB
This pin is the output of the Northbridge controller error amplifier.
46
FB_NB
This pin is the output voltage feedback to the inverting input of the Northbridge controller
error amplifier.
47
VCC
The bias supply for the IC’s control circuitry. Connect this pin to a +5V supply and
decouple using a quality 0.1µF ceramic capacitor.
48 VIN Battery supply voltage. It is used for input voltage feed-forward to improve the input line
transient performance.
-
GND
The bias and reference ground for the IC. The GND connection for the ISL6265C is
through the thermal pad on the bottom of the package.
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