9290X01.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 9290X01 데이타시트 다운로드

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DIGITAL SIGNAL PROCESSOR FOR CDP
PRELIMINARY
S5L9290X
INTRODUCTION
S5L9290X is a signal processing LSI for the CD. Digital processing function
(EFM demodulation, error correction), spindle motor servo processing, wide
capture range DPLL and 1-bit DAC for the CD player are installed in
S5L9290X.
48-LQFP-0707
FEATURES
• Signal processing part
— EFM data demodulation
— Frame sync detection, protection, insertion
— Sub code data processing (Q data CRC check, Q data register installed)
— Error correction (C1: 2 error correction, C2: 4 erasure correction)
— Installed 16K SRAM for De-interleave
— Interpolation
— Digital audio interface
— CLV servo control (X1, X2)
— Wide capture range digital PLL ( ± 50%)
• Digital filter, DAC part
— 4 times over sampling digital filter
— Digital de-emphasis (can be process the 32kHz, 44.1kHz, 48kHz)
— Sigma-delta stereo DAC installed
— Audio L.P.F installed
ORDERING INFORMATION
Device
S5L9290X01L0R0
Package
48-LQFP-0707
Supply Voltage
2.7V 3.3V (Analog, Internal logic)
2.7V 5.5V (I/O port)
Operating Temperature
-20°C +75°C
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PRELIMINARY
S5L9290X
BLOCK DIAGRAM
DIGITAL SIGNAL PROCESSOR FOR CDP
VCO1LF
EFMI
LOCK
SMEF
SMDP
SMDS
WDCK
WFCK
RFCK
C4M
XIN
ISTAT
MLT
MDAT
MCK
MUTE
DPLL
CLV
Servo
Timing
Generator
Micom
Interface
SOS1
SQCK SQDT
SBCK SBDT
Subcode
Out
EFM
Demodulator
ECC
16K
SRAM
Address
Generator
JITB
C2PO
DATX
Digital
Out
Interpolator
Digital
Filter
1-bit
DAC
I/O
Interface
PWM
LPF
SADTO
LRCKO
BCKO
SADTI
LRCKI
BCKI
LCHOUT VHALF
RCHOUT VREF
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DIGITAL SIGNAL PROCESSOR FOR CDP
PIN CONFIGURATION
PRELIMINARY
S5L9290X
VSSA_PLL 1
VCO1LF 2
VSSD_PLL 3
VDDD_PLL 4
VDDD1_5V 5
XIN 6
XOUT 7
VSSD1_5V 8
EFMI 9
LOCK 10
SMEF 11
SMON 12
48 47 46 45 44 43 42 41 40 39 38 37
S5L9290X
DSP+DAC
48-LQFP-0707
13 14 15 16 17 18 19 20 21 22 23 24
36 BCKO
35 LRCKO
34 SADTO
33 DATX
32 C2PO
31 JITB
30 SBCK
29 VDDD3-5V
28 VSSD2-3V
27 VDDD2-3V
26 MUTE
25 SQDT
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PRELIMINARY
S5L9290X
PIN DESCRIPTION
DIGITAL SIGNAL PROCESSOR FOR CDP
Table 1. Pin Description
NO. NAME
I/O
Pin Description
1 VSSA_PLL - Analog Ground for DPLL
2 VCO1LF O Pump out for VCO1
3 VSSD_PLL - Digital Ground Separated Bulk Bias for DPLL
4 VDDD_PLL - Digital Power Separated Bulk Bias for DPLL (3V Power)
5 VDDD1-5V - Digital Power (5V Power, I/O PAD)
6 XIN I X'tal oscillator input (16.9344MHz)
7 XOUT O X'tal oscillator output
8 VSSD1 - Digital Ground (I/O PAD)
9 EFMI
I EFM signal input
10 LOCK O CLV Servo locking status output
11 SMEF O LPF time constant control of the spindle servo error signal
12 SMDP O Phase control output for Spindle Motor drive
13 SMDS O Speed control output for Spindle Motor drive
14 WDCK O Word clock output (Normal Speed : 88.2KHz, Double Speed : 176.4KHz)
15 TESTV
I Various Data/Clock Input
16 LKFS O The Lock status output of frame sync
17 C4M O 4.2336MHz clock output
18 RESETB
I System Reset at 'L'
19 MLT
I Latch signal input from Micom
20 MDAT
I Serial data input from Micom
21 MCK
I Serial data receiving clock input from Micom
22 ISTAT O The internal status output to Micom
23 S0S1 O Subcode sync signal(S0+S1) output
24 SQCK
I Subcode-Q data transfering bit clock input
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DIGITAL SIGNAL PROCESSOR FOR CDP
NO. NAME
25 SQDT
26 MUTE
27 VDDD2-3V
28 VSSD2
28 VDDD3-5V
30 SBCK
31 JITB
32 C2PO
33 DATX
34 SADTO
35 LRCKO
36 BCKO
37 BCKI
38 LRCKI
39 SADTI
40 VSSD_DAC
41 VDDD_DAC
42 RCHOUT
43 VSSA_DAC
44 VREF
45 VHALF
46 VDDA_DAC
47 LCHOUT
48 VDDA_PLL
Table 1. Pin Description (continued)
I/O Function Description
O Subcode-Q data serial output
I System mute at 'H'
- Digital Power (3V Power, Internal Logic)
- Digital Ground (Internal Logic)
- Digital Power (5V Power, I/O PAD)
I Subcode data transfering bit clock
O Internal SRAM jitter margin status output
O C2 pointer output
O Digital audio data output
O Serial audio data output (48 slot, MSB first)
O Channel clock output
O Bit clock output
I Bit clock input
I Channel clock input
I Serial audio data input (48 slot, MSB first)
- Digital Ground for DAC
- Digital Power for DAC (3V Power)
O Right-Channel audio output through DAC
- Analog Ground for DAC
O Referance Voltage output for bypass
O Referance Voltage output for bypass
- Analog Power for DAC (3V Power)
O Left-Channel audio output through DAC
- Analog Power for PLL (3V Power)
PRELIMINARY
S5L9290X
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