X76F101.pdf 데이터시트 (총 17 페이지) - 파일 다운로드 X76F101 데이타시트 다운로드

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This X76F101 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
1K X76F101
ICmicTM
IC MICROSYSTEMS
128 x 8 bit
Secure SerialFlash
FEATURES
•64-bit Password Security
•One Array (112 Bytes) Two Passwords
—Read Password
—Write Password
•Programmable Passwords
•32-bit Response to Reset (RST Input)
•8 byte Sector Write mode
•1MHz Clock Rate
•2 wire Serial Interface
•Low Power CMOS
—3.0 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
•High Reliability Endurance:
—100,000 Write Cycles
•Data Retention: 100 years
•Available in:
—8 lead PDIP, SOIC, MSOP and ISO Card
—SmartCard Module
DESCRIPTION
The X76F101 is a Password Access Security Supervisor,
containing one 896-bit Secure Serial Flash array. Access
to the memory array can be controlled by two 64-bit
passwords. These passwords protect read and write
operations of the memory array.
The X76F101 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirectional
data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
The X76F101 also features a synchronous response to reset
providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
The X76F101 utilizes Xicor’s proprietary Direct WrTitMe
cell, providing a minimum endurance of 100,000 cycles and
a minimum data retention of 100 years.
Functional Diagram
CS
SCL
SDA
Interface
Logic
RST
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CHIP ENABLE
DATA TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RESET
RESPONSE REGISTER
8K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
112 Byte
32 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
RETRY COUNTER
7025 FM 01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7065 -1.1 4/17/98 T2/C0/D0 SH
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Characteristics subject to change without notice

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X76F101
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. During a
read cycle, data is shifted out on this pin. During a write
cycle, data is shifted in on this pin. In all other cases, this pin is
in a high impedance state.
Chip Select (CS)
When CS is high, the X76F101 is deselected and the
SDA pin is at high impedance and unless an internal
write operation is underway, the X76F101 will be in
standby mode. CS low enables the X76F101, placing it in
the active mode.
Reset (RST)
RST is a device reset pin. When RST is pulsed high
while CS is low the X76F101 will output 32 bits of fixed
data which conforms to the standard for “synchronous
response to reset”. CS must remain LOW and the part
must not be in a write cycle for the response to reset to occur.
See Figure 7. If at any time during the response to
reset CS goes HIGH, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
DEVICE OPERATION
The X76F101 memory array consists of fourteen 8-byte
sectors. Read or write access to the array always begins
at the first address of the sector. Read operations then can
continue indefinitely. Write operations must total 8
bytes.
There are two primary modes of operation for the
X76F101; Protected READ and protected WRITE.
Protected operations must be performed with one of two
8-byte passwords.
The basic method of communication for the device is
established by first enabling the device (CS LOW),
generating a start condition, then transmitting a command,
www.DfoalltoawShedeebt4yUth.ceocmorrect password. All parts will
be shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer (see
Acknowledge Polling.) Only after the correct
password is accepted and a ACK polling has been
performed, can the data transfer occur.
To ensure the correct communication, RST must remain LOW
under all conditions except when running a
“Response to Reset sequence”.
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
If the X76F101 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to
loading of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be
terminated and the part will reset and enter into a
standby mode.
The basic sequence is illustrated in Figure 1.
PIN NAMES
Symbol
CS
SDA
SCL
RST
Vcc
Vss
NC
Description
Chip Select Input
Serial Data Input/Output
Serial Clock Input
Reset Input
Supply Voltage
Ground
No Connect
PIN CONFIGURATION
VCC
NC
NC
Vss
PDIP
18
27
36
45
RST
SCL
SDA
CS
VSS
CS
SDA
NC
SOIC
18
27
36
45
VCC
RST
SCL
NC
VSS
NC
CS
SDA
MSOP
18
27
36
45
VCC
NC
RST
SCL
Smart Card
VCC
RST
SCL
NC
GND
CS
SDA
NC
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X76F101
After each transaction is completed, the X76F101 will reset
and enter into a standby mode. This will also be the
response if an unsuccessful attempt is made to access a
protected array.
Figure 1. X76F101 Device Operation
LOAD COMMAND/ADDRESS BYTE
LOAD 8-BYTE
PASSWORD
VERIFY PASSWORD
ACCEPTANCE BY
USE OF ACK POLLING
READ/WRITE
DATA
BYTES
Device Protocol
The X76F101 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as a
receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master will
always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
X76F101 will be considered a slave in all applications.
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start
cannot be generated while the part is outputting data.
Starts are inhibited while a write is in progress.
Stop Condition
All communications must be terminated by a stop
condition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data input
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received the
eight bits of data.
The X76F101 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F101 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
Start Condition
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All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F101 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
any command until this condition is met.
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X76F101
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
Table 1. X76F101 Instruction Set
Command
after Start
1 0 0 S3 S2 S1 S00
1 0 0 S3 S2 S1 S0 1
11111100
11111110
01010101
Command Description
Sector Write
Sector Read
Change Write Password
Change Read Password
Password ACK Command
Password
used
Write
Read
Write
Write
None
Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to the
standby mode. All write/read operations require a password.
PROGRAM OPERATIONS
Sector Write
The sector write mode requires issuing the 8-bit write
www.DcoamtamSahnedet4foUll.ocwomed by the password and then the data
bytes transferred as illustrated in figure 4. The write
command byte contains the address of the sector to be
written. Data is written starting at the first address of a sector
and eight bytes must be transferred. After the last
byte to be transferred is acknowledged a stop condition is
issued which starts the nonvolatile write cycle. If more or less
than 8 bytes are transferred, the data in the sector
remains unchanged.
ACK Polling
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F101 initiates the internal
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can begin
immediately. This involves issuing the start condition
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X76F101
followed by the new command code of 8 bits (1st byte of the
protocol.) If the X76F101 is still busy with the
nonvolatile write operation, it will issue a “no-ACK” in
response. If the nonvolatile write operation has
completed, an “ACK” will be returned and the host can then
proceed with the rest of the protocol.
Password ACK Polling Sequence
PASSWORD LOAD
COMPLETED
ENTER ACK POLLING
Data ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ENTER ACK POLLING
ISSUE START
ISSUE NEW
COMMAND
CODE
ISSUE START
ISSUE
PASSWORD
ACK COMMAND
ACK
RETURNED?
YES
NO
ACK
RETURNED?
NO
PROCEED
YES
PROCEED
After the password sequence, there is always a nonvolatile
write cycle. This is done to discourage random
guesses of the password if the device is being tampered with.
In order to continue the transaction, the X76F101
requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As
with regular Acknowledge polling the user can either time out
for 10ms, and then issue the ACK polling once, or
continuously loop as described in the flow.
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle in
response to the password ACK polling sequence is over.
If the password that was inserted was incorrect, then a “no
www.DAaCtaKShweiellt4bUe .rceotmurned even if the nonvolatile cycle is
over. Therefore, the user cannot be certain that the pass-
word is incorrect until the 10ms write cycle time has
elapsed.
READ OPERATIONS
Read operations are initiated in the same manner as write
operations but with a different command code.
Sector Read
With sector read, a sector address is supplied with the read
command. Once the password has been
acknowledged data may be read from the sector. An
acknowledge must follow each 8-bit data transfer. A read
operation always begins at the first byte in the sector, but may
stop at any time. Random accesses to the array are
not possible. Continuous reading from the array will return
data from successive sectors. After reading the
last sector in the array, the address is automatically set to the
first sector in the array and data can continue to be
read out. After the last bit has been read, a stop condition is
generated without sending a preceding acknowledge.
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