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DEVICES INCORPORATED
DEVICES INCORPORATED
L10C11
L10C114/8-bit Variable Length Shift Register
4/8-bit Variable Length Shift Register
FEATURES
DESCRIPTION
u Variable Length 4 or 8-bit Wide
Shift Register
u Selectable Delay Length from 3 to
18 Stages
u Low Power CMOS Technology
u Replaces Fairchild TMC2011
u Load, Shift, and Hold Instructions
u Separate Data In and Data Out Pins
u Package Styles Available:
• 24-pin Plastic DIP
• 28-pin Plastic LCC, J-Lead
The L10C11 is a high-speed, low
power CMOS variable length shift
register. The L10C11 consists of two
4-bit wide, adjustable length shift
registers. These registers share control
signals and a common clock. Both
shift registers can be programmed
together to any length from 3 to 18
stages inclusive, or one register can be
fixed at 18 stages of delay while the
other is variable. The configuration
implemented is determined by the
Length Code (L3-0) and the MODE
control line as shown in Table 1.
Each input is applied to a chain of
registers which are clocked on the
rising edge of the common CLK input.
These registers are numbered R1
through R17 and R1’ through R17’,
corresponding to the D3-0 and D7-4
data fields respectively. A multi-
plexer serves to route the contents of
any of registers R2 through R17 to the
output register, denoted R18. A
similar multiplexer operates on the
contents of R2’ through R17’ to load
R18’. Note that the minimum-length
path from data inputs to outputs is R1
to R2 to R18, consisting of three stages
of delay.
The MODE input determines whether
one or both of the internal shift
registers have variable length. When
MODE = 0, both D3-0 and D7-4 are
delayed by an amount which is
controlled by L3-0. When MODE = 1,
the D7-4 field is delayed by 18 stages
independent of L3-0.
The Length Code (L3-0) controls the
number of stages of delay applied to
the D inputs as shown in Table 1.
When the Length Code is 0, the inputs
are delayed by 3 clock periods. When
the Length Code is 1, the delay is 4
clock periods, and so forth. The
Length Code and MODE inputs are
latched on the rising edge of CLK.
Both the Length Code and MODE
values may be changed at any time
without affecting the contents of
registers R1 through R17 or R1’
through R17’.
L10C11 BLOCK DIAGRAM
D3-0
CLK
L3-0
4
4
R17
R16
R15
4
Y3-0
R4
R3
R2
MODE
D7-4
4
R17’
R16’
R15’
R4’
R3’
R2’
4
Y7-4
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DEVICES INCORPORATED
L10C11
4/8-bit Variable Length Shift Register
TABLE 1. CONTROL ENCODING
Length Code Mode = 0 Mode = 1
Delay
Delay
L3 L2 L1 L0 Y3-0 Y7-4 Y3-0 Y7-4
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
33
44
55
66
77
88
99
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
3 18
4 18
5 18
6 18
7 18
8 18
9 18
10 18
11 18
12 18
13 18
14 18
15 18
16 18
17 18
18 18
MAXIMUM RATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ..................................................... –65°C to +150°C
Operating ambient temperature ..................................... –55°C to +125°C
VCC supply voltage with respect to ground ...................... –0.5 V to +7.0 V
Input signal with respect to ground .................................. –3.0 V to +7.0 V
Signal applied to high impedance output ......................... –3.0 V to +7.0 V
Output current into low outputs ....................................................... 25 mA
Latchup current ......................................................................... > 400 mA
OPERATING CONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Com.
Active Operation, Mil.
Temperature Range
0°C to +70°C
–55°C to +125°C
Supply Voltage
4.75 V £ VCC £ 5.25 V
4.50 V £ VCC £ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
VOH Output High Voltage
VCC = Min., IOH = –12 mA
VOL Output Low Voltage
VCC = Min., IOL = 24 mA
VIH Input High Voltage
VIL Input Low Voltage
(Note 3)
IIX Input Current
Ground VIN VCC (Note 12)
ICC1 VCC Current, Dynamic
(Notes 5, 6)
ICC2 VCC Current, Quiescent (Note 7)
Min Typ Max Unit
2.4 V
0.5 V
2.0 VCC V
0.0 0.8 V
±20 µA
10 20 mA
1.0 mA
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DEVICES INCORPORATED
L10C11
4/8-bit Variable Length Shift Register
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol Parameter
tPD Output Delay
tPW Clock Pulse Width
tSD Data Setup Time
tHD Data Hold Time
tSL L3-0, MODE Setup Time
tHL L3-0, MODE Hold Time
111111111111111111111111112222222222222222222222222233333333333333333333333333M12244444444444444444444444444i225005555555555555555555555555n6666666666666666666666666677777777777777777777777777288888888888888888888888888599999999999999999999999999*00000000000000000000000000M11111111111111111111111111222222222222222222222222222a533333333333333333333333333x444444444444444444444444445555555555555555555555555566666666666666666666666666
L10C11–
20
Min Max
20
12
10
0
10
0
15
Min Max
15
10
8
0
8
0
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
Symbol Parameter
tPD Output Delay
tPW Clock Pulse Width
tSD Data Setup Time
tHD Data Hold Time
tSL L3-0, MODE Setup Time
tHL L3-0, MODE Hold Time
111111111111111111111111112222222222222222222222222233333333333333333333333333M12244444444444444444444444444i22555555555555555555555555555n6666666666666666666666666677777777777777777777777777388888888888888888888888888099999999999999999999999999*00000000000000000000000000M11111111111111111111111111322222222222222222222222222a033333333333333333333333333x4444444444444444444444444455555555555555555555555555666666666666666666666666667777777777777777777777777788888888888888888888888888M9999999999999999999999999911100000000000000000000000000Li2022n111111111111111111111111111222222222222222222222222220233333333333333333333333333C544444444444444444444444444*155555555555555555555555555166666666666666666666666666M277777777777777777777777777a588888888888888888888888888x9999999999999999999999999900000000000000000000000000111111111111111111111111112222222222222222222222222211111111111111111111111111M2222222222222222222222222211133333333333333333333333333i00200n4444444444444444444444444455555555555555555555555555266666666666666666666666666077777777777777777777777777*8888888888888888888888888899999999999999999999999999M200000000000000000000000000a011111111111111111111111111x222222222222222222222222223333333333333333333333333344444444444444444444444444
SWITCHING WAVEFORMS
D7-0
L3-0
MODE
CLK
Y7-0
tSD
tSL
tHD
tHL
tPW
tPD
tPW
1111*2222D3333I4444S5555C6666O7777N8888TI9999N0000U1111E2222D3333S4444P5555E6666E7777D88889999G0000R1111A2222D3333E4444
3
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DEVICES INCORPORATED
L10C11
4/8-bit Variable Length Shift Register
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values be-
yond those indicated in the Operating
Conditions table is not implied. Expo-
sure to maximum rating conditions for
extended periods may affect reliability.
2. The products described by this speci-
fication include internal circuitry de-
signedtoprotect the chipfrom damaging
substrate injection currents and accumu-
lations of static charge. Nevertheless,
conventional precautions should be ob-
served during storage, handling, and use
of these circuits in order to avoid expo-
sure to excessive electrical stress values.
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given application
can be accurately approximated by:
where
NCV2 F
4
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
CL
IOL
VTH
IOH
FIGURE B. THRESHOLD LEVELS
tENA
tDIS
OE 1.5 V
1.5 V
Z0
1.5 V
VOL* 0.2 V
3.5V Vth
0Z
Z1
1.5 V
VOH* 0.2 V
1Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
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DEVICES INCORPORATED
ORDERING INFORMATION
24-pin — 0.3" wide
D0
D1
D2
D3
L0
L1
VCC
CLK
D4
D5
D6
D7
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 16
10 15
11 14
12 13
Y0
Y1
Y2
Y3
L2
L3
GND
MODE
Y4
Y5
Y6
Y7
Speed
Plastic DIP
(P2)
0°C to +70°C — COMMERCIAL SCREENING
20 ns
15 ns
L10C11PC20
L10C11PC15
–55°C to +125°C — COMMERCIAL SCREENING
L10C11
4/8-bit Variable Length Shift Register
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Plastic DIP
(P1)
–55°C to +125°C — MIL-STD-883 COMPLIANT
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