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ST8016
160 Output LCD Common/ Segment Driver IC
Datasheet
Version 2.0
2008/05/07
Note: Sitronix Technology Corp. reserves
the right to change the contents in this
document without prior notice. This is not
a final specification. Some parameters
are subject to change.
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ST8016
1 FEATURES
n Number of LCD drive outputs: 160
n Supply voltage for LCD drive: +15.0 to +30.0 V
n Supply voltage for the logic system: +2.5 to +5.5 V
n Low power consumption
n Low output impedance
(Segment mode)
n Shift clock frequency
- 20 MHz (MAX.): VDD = +5.0 ± 0.5 V
- 12 MHz (MAX.): VDD = +3.0 to + 4.5 V
- 8 MHz (MAX.): VDD = +2.5 to + 3.0 V
n Adopts a data bus system
n 4-bit/8-bit parallel input modes are
selectable with a mode (MD) pin
n Automatic transfer function of an
enable signal
n Automatic counting function which, in
the chip selection mode, causes the
internal clock to be stopped by
automatically counting 160 bits of input
data
n Line latch circuits are reset when
/DISPOFF active
(Common mode)
n Shift clock frequency: 4 MHz (MAX.)
n Built-in 160-bit bi-directional shift
register (divisible into 80 bits x 2)
n Available in a single mode (160-bit shift
register) or in a dual mode (80-bit shift
register x 2)
- Y1->Y160 Single mode
- Y160->Y1 Single mode
- Y1->Y80, Y81->Y160 Dual mode
- Y160->Y81, Y80->Y1 Dual mode
The above 4 shift directions are
pin-selectable
n Shift register circuits are reset when
/DISPOFF active
2 DESCRIPTION
The ST8016 is a 160-output segment/common driver IC suitable for driving large/medium scale dot
matrix LCD panels, and is used in personal computers/work stations. Through the use of SST
(Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of
the LCD module. The ST8016 is good both as a segment driver and a common driver, and it can
create a low power consuming, high-resolution LCD.
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Ver 2.0
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2008/05/07

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3 PIN CONNECTIONS
ST8016
186 PIN TCP
Y1 1
Y2
Y3
Y158
Y159
Y160
160
186 V0R
V12R
V43R
VSS
MD
FR
EIO1
LP
/DISPOFF
XCK
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
EIO2
S/C
VDD
L/R
VSS
V43L
V12L
161 V0L
Package: 186-pin TCP (Tape Carrier Package)
4 PIN DESCRIPTION (TCP)
PIN NO.
1 ~ 160
161,186
162,185
163,184
165
166
167
168,180
169 ~ 175
176
177
178
179
181
182
164,183
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SYMBOL
Y1-Y160
V0L, V0R
V12L, V12R
V43L, V43R
L/R
VDD
S/C
EIO2, EIO1
DI0-DI6
DI7
XCK
/DISPOFF
LP
FR
MD
VSS
I/O DESCRIPTION
O LCD drive output
P Power supply for LCD drive
P Power supply for LCD drive
P Power supply for LCD drive
I Display data shift direction selection
P Power supply for logic system (+2.5 to +5.5 V)
I Segment mode/common mode selection
I/O
Input/output for chip selection at segment mode
Shift data input/output for shift register at common mode
I Display data input at segment mode
I
Display data input at segment mode/Dual mode data input at common
mode
I Clock input for taking display data at segment mode
I Control input for output of non-select level
I
Latch pulse input for display data at segment mode/
Shift clock input for shift register at common mode
I AC-converting signal input for LCD drive waveform
I Mode selection input
P Ground (0 V)
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5 BLOCK DIAGRAM
V0R V12R V43R
Y1 Y2
Y159 Y160
FR
DISPOFF
EIO1
EIO2
LP
XCK
L/R
MD
S/C
LEVEL
SHIFTER
ACTIVE
CONTROL
CONTROL LOGIC
8
160-BIT 4-LEVEL DRIVER
160
160-BIT LEVEL SHIFTER
160
160-BIT LINE LATCH/SHIFT REGISTER
16 16
16
8 BIT
DATA
LATCH
DATA LATCH CONTROL
SP CONVERSION & DATA CONTROL
(4 to 8 or 8 to 8)
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
VDD VSS
ST8016
V43L
V12L
V0L
6 FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
In case of segment mode, controls the selection or non-selection of the chip.
Following an LP signal input, and after the chip selection signal is input, a selection signal
Active Control
is generated internally until 160 bits of data have been read in.
Once data input has been completed, a selection signal for cascade connection is output,
and the chip is non-selected.
In case of common mode, controls the input/output data of bi-directional pins.
SP Conversion
& Data Control
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel
input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel
input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time.
In case of segment mode, selects the state of the data latch which reads in the data bus
Data Latch Control signals. The shift direction is controlled by the control logic. For every 16 bits of data read
in, the selection signal shifts one bit based on the state of the control circuit.
In case of segment mode, latches the data on the data bus. The latch state of each LCD
Data Latch
drive output pin is controlled by the control logic and the data latch control; 160 bits of
data are read in 20 sets of 8 bits.
In case of segment mode, all 160 bits which have been read into the data latch are
Line Latch/
simultaneously latched at the falling edge of the LP signal, and are output to the level
Shift Register
shifter block. In case of common mode, shifts data from the data input pin at the falling
edge of the LP signal.
Level Shifter
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the
driver block.
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Drives the LCD drive output pins from the line latch/shift register data, and selects one of
4 levels (V0, V12, V43 or VSS) based on the S/C, FR and /DISPOFF signals.
Controls the operation of each block. In case of segment mode, when an LP signal has
been input, all blocks are reset and the control logic waits for the selection signal output
Control Logic
from the active control block. Once the selection signal has been output, operation of the
data latch and data transmission is controlled, 160 bits of data are read in, and the chip is
non-selected. In case of common mode, controls the direction of data shift.
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7 INPUT/ OUTPUT CIRCUITS
V DD
ST8016
I
Vss (0V)
V DD
To Internal Circuit
Applicable Pins
L/R , S/C , DI6~DI0 ,
DISPOFF , LP , FR , MD
FIGURE 7-1 Input Circuit (1)
I To Internal Circuit
Control Signal
Applicable Pins
DI7 , XCK
Vss (0V)
V DD
Vss (0V)
FIGURE 7-2 Input Circuit (2)
I
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Vss (0V)
VDD
Vss (0V)
FIGURE 7-3 Input Circuit (3)
To Internal Circuit
Applicable Pins
TEST1 , TEST2
Ver 2.0
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2008/05/07