The UTC L11815B of CMOS regulators insist of a PMOS pass transistor, voltage reference, error amplifier,
over-current protection, and thermal shutdown.
The error amplifier, over-current shutdown, and thermal protection circuits provides data for P-channel pass
transistor. The error amplifier takes output voltage for a precision reference in the normal operation and the normal
operation is restored when the junction temperature drops below 120°C. Over-current and Thermal shutdown circuits
start to work when the junction temperature is higher than 140°C, or the current is higher than 2.2A. The output
voltage stays low when the thermal shutdown is in active.
The UTC L11815B behaves like a current source when the load reaches 2.2A. But the current would fall back to
600mA to prevent excessive power loss when the load impedance value is below 0.3Ω.Normal operation is restored
when the load resistance value is higher than 0.75 Ω.
The UTC L11815B has an output capacitor to ground of 4.7μF or more in the stable operation. Ceramic
capacitors can provide the lowest ESR with the best AC performance. Aluminum Electrolytic capacitors, in contrast,
have the highest ESR with poorest AC response. Unfortunately, large value ceramic capacitors are comparatively
expensive. So we can parallel a 0.1μF ceramic capacitor with a 10μF Aluminum Electrolytic. The result is low ESR,
high capacitance, and low overall cost.
A second capacitor is recommended between the input and ground to stabilize input voltage. To get an ideal
effect the value of the input capacitor should be at least 0.1μF.
A third capacitor can be connected between the bypass pin and ground. This capacitor can be a low cost
Polyester Film varies in the range of 0.001 ~ 0.01μF. A larger capacitor improves the AC ripple rejection, but also
makes the output come up slowly. This "Soft" turn-on is desirable in some applications to limit turn-on surges.
At last, all the capacitors should keep a close proximity to the pins; you can achieve this with a star connection.
When pulled low, the PMOS pass transistor shuts off, and all internal circuits are powered down. In this state, the
quiescent current is less than 1μA. This pin behaves much like an electronic switch.
100kΩ resistor is necessary between VEN source and EN pin when VEN is higher than VIN.
(Note: There is no internal pull-up for EN PIN.)
The adjustable version uses external feedback resistors to generate an output voltage anywhere from 1.5V to
5.0V. VADJ is trimmed to 1.2V and VOUT is given by the equation:
VOUT = VADJ (1 + R1 / R2)
Feedback resistors R1 and R2 should be high enough to keep quiescent current low, but increasing R1 + R2 will
reduce stability. In general, R1 and R2 in the 10’s of kΩ will produce adequate stability, given reasonable layout
precautions. To improve stability characteristics, keep parasitics on the ADJ pin to a minimum, and lower R1 and R2
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