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V103
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
General Description
The V103 LVDS display interface transmitter is
primarily designed to support pixel data transmission
between a video processing engine and a digital video
display. The data rate supports up to SXGA+
resolutions and can be used in Plasma, Rear Projector,
Front Projector, CRT and LCD display applications. It
can also be used in other high-bandwidth parallel data
applications and provides a low EMI interconnect over
a low cost, low bus width cable up to several meters in
length.
The V103 converts 35 bits of CMOS/TTL data, clocked
on the rising or falling edge of an input clock
(selectable), into six LVDS (Low Voltage Differential
Signaling) serial data stream pairs. In video
applications the 35 bits is normally divided into 10 bits
for each R, G and B channel and 5 control bits.
When combined with the V104 LVDS display interface
receiver, the V103 + V104 combination provides a
35-bit wide, 90 MHz transport. The rate of each LVDS
channel is 630 Mbps for a 90MHz data input clock, 945
Mbps for 135MHz.
Features
Pin compatible with THine THC63LVD103
Wide pixel clock range: 8 - 135 MHz
Supports a wide range of video and graphics modes
including VGA, SVGA, XGA, SXGA, SXGA+, NTSC,
PAL, SDTV, and HDTV up to 1080I or 720P
Internal PLL requires no external loop filter
Selectable rising or falling clock edge for data
alignment
Compatible with Spread Spectrum clock source
Reduced LVDS output voltage swing mode
(selectable) to minimize EMI
CMOS/TTL data inputs can be configured for
reduced input voltage swing
Single 3.3 V supply
Low power consumption CMOS design
Power down mode
64-pin TQFP lead free package
Block Diagram
TA0-6
TB0-6
TC0-6
TD0-6
TE0-6
RS
R/F
/PWDN
7
7
7
7
7
Parallel
to Serial
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CLKIN
(8 to 135 MHz)
PLL
TA+
TA-
TB+
TB-
TC+
TC-
TD+
TD-
TE+
TE-
TCLK+
TCLK-
V103 Datasheet
1
11/23/06
Revision 2.0
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

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V103
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Pin Assignment
TD5
GND
TD6
TE0
TE1
TE2
VCC
TE3
TE4
GND
TE5
CLKIN
/PWDN
PLLGND
PLLVCC
TE6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-pin TQFP
48 TB5
47 GND
46 TB4
45 TB3
44 TB2
43 RS
42 TB1
41 TB0
40 TA6
39 GND
38 TA5
37 TA4
36 TA3
35 TA2
34 TA1
33 TA0
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V103 Datasheet
2
11/23/06
Revision 2.0
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

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V103
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
30, 31
TA+, TA-
28, 29
TB+, TB-
24, 25
TC+, TC- LVDS OUT LVDS Serial Data Output Pairs
20, 21
TD+, TD-
18, 19
TE+, TE-
22, 23
TCLK+, TCLK- LVDS OUT LVDS Reference Clock Output Pair
33, 34, 35, 36,
37, 38, 40
TA0 ~ TA6
41, 42, 44, 45,
46, 48, 49
TB0 ~ TB6
50, 52, 53, 54,
55, 57, 58
TC0 ~ TC6
IN CMOS/TTL (or small signal) Data Bit Inputs
59, 61, 62, 63,
64, 1, 3
TD0 ~ TD6
4, 5, 6, 8, 9, 11,
16
TE0 ~ TE6
13
/PWDN
IN High: Normal device operation
Low: Power down; all outputs become high impedance
43 RS IN Voltage level on this pin sets LVDS output swing voltage and data input
swing voltage; refer to the table at the bottom of this page.
60 R/F IN Input Clock triggering edge select. High: Rising edge; Low: Falling edge.
51, 7
VCC
Power Power supply pins for TTL inputs and digital circuitry.
12
CLKIN
IN Clock Input.
2, 10, 39, 47,
56
GND
Ground Ground pins for TTL inputs and digital circuitry.
27
LVDSVCC
Power Power supply pins for LVDS outputs.
17, 26, 32
LVDSGND
Ground Ground pins for LVDS outputs.
15
PLLVCC
Power Power supply pin for PLL circuitry.
14
PLLGND
Ground Ground pin for PLL circuitry.
RS Input Voltage Configuration to set LVDS Output Swing and Data Input Swing
RS Input Voltage
VCC
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GND
LVDS Output Swing
350 mV
350 mV
200 mV
CMOS/TTL Input Configuration (Input Voltage Swing)
Standard Configuration1
Small Input Swing Configuration1
Standard Configuration1
Note 1: Refer to DC Electrical Characteristics.
V103 Datasheet
3
11/23/06
Revision 2.0
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

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V103
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
External Components
Decoupling capacitors should be used for all power pins. The V103 requires no other external components.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V103. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VCC
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Driver Output Voltage
Storage Temperature
Junction Temperature
Soldering Temperature (10 seconds)
Maximum Power Dissipation @ 25°C
Rating
-0.3 V to +4.0 V
-0.3 V to VCC+0.3 V
-0.3 V to VCC+0.3 V
-0.3 V to VCC+0.3 V
-55 to +150°C
120°C
260°C
1.0 W
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
+3.3
Max.
+70
+3.6
Units
°C
V
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V103 Datasheet
4
11/23/06
Revision 2.0
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

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V103
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
DC Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature 0 to +70°C
Parameter
Symbol
Conditions
Min.
Typ. Max.
CMOS/TTL Inputs, Standard Configuration
Input High Voltage
VIH RS=VCC or GND
Input Low Voltage
VIL RS=VCC or GND
Input Current
IINC 0V<VIN<VCC
CMOS/TTL Inputs, Small Input Swing Configuration
Max Input Swing Voltage
Input Reference Voltage into pin RS
High Level Input Voltage
(for small input swing condition)
VDDQ1
VREF
VSH2
VREF = VRS = VDDQ/2
VREF=VDDQ/2
Low Level Input Voltage
(for small input swing condition)
VSL2
VREF=VDDQ/2
2.00
GND
VCC
0.80
±10
1.2
VDDQ/2
+0.1V
VDDQ/2
2.8
VDDQ/2
-0.1V
Note 1: VDDQ voltage defines the max voltage of the small swing input and is not an actual input into the device.
Note 2: Small input swing voltage is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0], and CLKIN.
Units
V
V
µA
V
V
V
V
LVDS Transmitter DC Specifications
Differential Output Voltage,
RL = 100
Change in VOD Between Complimentary
Output States
Common Mode Voltage
Change in VOC Between Complimentary
Output States
Output Short Circuit Current
Output Tri-State Current
VOD
DVOD
Normal swing
RS = VCC
Reduced swing
RS = GND
VOC
DVOC
RL = 100
IOS VOUT = 0V, RL = 100
IOZ /PWDN = 0V,
VOUT = 0V to VCC
250
100
1.125
350
200
1.250
450
300
35
1.375
35
-24
±10
mV
mV
mV
V
mV
mA
µA
Supply Current
Transmitter Supply Current
Transmitter Supply Current
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Transmitter Power Down Supply Current
ITCCG
ITCCW
ITCCS
RL = 100, CL=5 pF,
f = 85 MHz
VCC = 3.3 V, RS = VCC f =135 MHz
Gray Scale Pattern
RL = 100, CL=5 pF,
f = 85 MHz
VCC = 3.3 V, RS = GND f =135 MHz
Gray Scale Pattern
RL = 100, CL = 5 pF,
f = 85 MHz
VCC = 3.3 V, RS = VCC f =135 MHz
Worst Case Pattern
RL = 100, CL= 5 pF,
f = 85 MHz
VCC = 3.3 V, RS = GND f =135 MHz
Worst Case Pattern
/PWDN = L
58
70
44
56
69
87
55
73
64 mA
76 mA
50 mA
62 mA
75 mA
93 mA
61 mA
79 mA
10 µA
V103 Datasheet
5
11/23/06
Revision 2.0
Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com