L4925.pdf 데이터시트 (총 8 페이지) - 파일 다운로드 L4925 데이타시트 다운로드

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® L4925
VERY LOW DROP VOLTAGE REGULATOR
OPERATING DC SUPPLY VOLTAGE RANGE
6V TO 28V
TRANSIENT SUPPLY VOLTAGE UP TO 40V
EXTREMELY LOW QUIESCENT CURRENT
HIGH PRECISION OUTPUT VOLTAGE
OUTPUT CURRENT CAPABILITY UP TO
500mA
VERY LOW DROPOUT VOLTAGE LESS
THAN 0.6V
RESET CIRCUIT SENSING THE OUTPUT
VOLTAGE
PROGRAMMABLE RESET PULSE DELAY
WITH EXTERNAL CAPACITOR
THERMAL SHUTDOWN AND SHORT CIR-
CUIT PROTECTIONS
DESCRIPTION
The L4925 is a monolithic integrated 5V voltage
regulator with a very low dropout output and addi-
BLOCK DIAGRAM
Pentawatt
PowerSO20
ORDERING NUMBERS: L4925 (Pentawatt)
L4925PD (PowerSO20)
tional functions such as power-on reset and pro-
grammable reset delay time. It is designed for
supplying microcomputer controlled systems es-
pecially in automotive applications.
VS
CS
PREREGULATOR
5V
Vz
+
-
GND
REG
VREF
1.23V
Vz
2µ
RESET
L4925N
= 2V
VO
CT
RES
D95AT151
June 2000
1/8
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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L4925
ABSOLUTE MAXIMUM RATINGS
Symbol
VSDC
VSTR
IO
VO
VRES
IRES
Tstg
Tj
Tj-SD
Parameter
DC Operating Supply Voltage
Transient Supply Voltage (t < 1s)
Output Current
Output Voltage
Output Voltage
Output Current
Storage Temperature
Operating Junction Temperature
Thermal Shutdown-Junction Temperature
Value
28
40
internally limited
20
20
5
-55 to 150
-40 to 150
165
Unit
V
V
V
V
mA
°C
°C
°C
NOTE:
The circuit is ESD protected according to MIL-STD-883C. According to ISO/DIS 7637 the transients must be clamped with external circuitry
(see Application Circuit).
CONNECTION DIAGRAM
N.C.
N.C.
VS
VS
N.C.
N.C.
RES
N.C.
N.C.
GND
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
D95AT152
N.C.
N.C.
N.C.
VOUT
VOUT
N.C.
CT
N.C.
N.C.
N.C.
THERMAL DATA
Symbol
Rth j-amb
Rth j-case
Parameter
Thermal resistance junction to ambient
Thermal resistance junction to case
2/8
max.
max.
Pentawatt
60
3.5
SO 20
77 to 97
Unit
°C/W
°C/W

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L4925
ELECTRICAL CHARACTERISTICS (VS =14V Tj =–40 to 125°C unless otherwise specified;
Symbol
VO
VO
VDP
VIO
VOL
VOLO
ILIM
IQSE
IQ
RESET
Parameter
Output Voltage
Output Voltage
Dropout Voltage
Input to Output Voltage
Difference in Undervoltage
Condition
Line Regulation
Load Regulation
Current Limit
Quiescent Current
Quiescent Current
Test Condition
VI = 6 to 28V; IO = 1 to 500mA
VI = 35V; T <1s;
IO = 1 to 500mA
IO = 100mA
IO = 500mA
VI = 4V; IO = 100mA
Min.
4.90
Typ.
5
0.2
0.3
Max.
5.10
5.50
0.3
0.6
0.5
VI = 6 to 28V; IO = 1 to 1mA
10
IO = 1 to 500mA
50
VO = 4.5V;
550 1000 1500
VO = 0; Foldback characteristic
250
IO = 0.3mA
190 360
IO = 500mA
20
Symbol
VRT
VRTH
tRD
tRR
VRL
IRH
VCTth
VCTth hy
Parameter
Reset Threshold Voltage
Reset Threshold
Reset Pulse Delay
Reset Reaction Time
Reset Output LOW Voltage
Reset Output HIGH Leakage
Current
Delay Comparator Threshold
Delay Comparator Threshold
Hysteresis
Test Condition
CT = 100nF; tR > 100µs
CT = 100nF;
RRES = 10Kto VO; VS => 3V
VRES = 5V
Min.
4.5
50
60
Typ.
100
100
5
Max.
5.2
200
140
30
0.4
1
2
200
Unit
V
V
V
V
V
mV
mV
mA
mA
µA
mA
Unit
V
mV
ms
µs
V
µA
V
mV
APPLICATION CIRCUIT DIAGRAM
VBAT
VS
CS
PREREGULATOR
5V
Vz
+
-
GND
REG
VREF
1.23V
Vz
2µ
RESET
L4925N
= 2V
Vo
Co
CT
RES
Vout
RES
D95AT153
For stability: CS > 1µF; CO > 10µF;ESR < 2.5at 10 KHz
Recommended for application: CS =CO = 10µF to 100µF
3/8

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L4925
APPLICATION NOTE
SUPPLY VOLTAGE TRANSIENTS
High supply voltage transients can cause a reset
output signal disturbation.
For supply voltage greater than 8V the circuit
shows a high immunity of the reset output against
supply transients of more than 100V/µs.
For supply voltage lower than 8V, supply tran-
sients of more than 0.4V/µs. can cause a reset
signal disturbation.
Foldback Characteristics Of Vo
FUNCTIONAL DESCRIPTION
The L4925 is a monolithic integrated voltage
regulator, based on the STM modular voltage
regulator approach. Several outstanding features
and auxiliary functions are implemented to meet
the requirements of supplying microprocessor
systems in automotive applications.
Nevetrheless, it is suitable also in other applica-
tions where the present functions are required.
The modular approach of this device allows to get
easily also other features and functions when re-
quired.
VOLTAGE REGULATOR
The voltage regulator uses an Isolated Collector
Vertical PNP transistor as a regulating element.
With this structure very low dropout voltage at
currents up to 500mA is obtained.
Figure 1: Output Voltage vs. Input Voltage
The dropout operation of the standby regulator is
maintained down to 3V input supply voltage. The
output voltage is regulated up to the transient in-
put supply voltage of 35V. With this feature no
functional interruption due to overvoltage pulses
is generated.
The typical curve showing the standby output
voltage as a function of the input supply voltage is
shown in fig. 1.
The current consumption of the device (quiescent
current) is less than 250µA.
To reduce the quiescent current peak in the un-
dervoltage region and to improve the transient re-
sponse in this region, the dropout voltage is con-
trolled.
The quiescent current as a function of the supply
input voltage is shown in fig. 2.
Figure 2: Quiescent Current vs. Supply Voltage
4/8

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L4925
RESET CIRCUIT
The block circuit diagram of the reset circuit is
shown in Figure 3. The reset circuit supervises
the output voltage. The reset threshold of 4.5V is
defined with the internal reference voltage and
standby output divider.
The reset pulse delay time tRD, is defined with the
charge time of an external capacitor CT:
tRD=CT2µxA2V
The reaction time of the reset circuit originates
from the discharge time limitation of the reset ca-
pacitor CT and it is proportional to the value of CT.
The reaction time of the reset circuit increases the
noise immunity.Standby output voltage drops be-
low the reset threshold only a bit longer than the
reaction time results in a shorter reset delay time.
The nominal reset delay time will be generated for
standby output voltage drops longer than approxi-
mately 50µs. The typical reset output waveforms
are shown in Figure 4.
Figure 3
Figure 4
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