YSS932.pdf 데이터시트 (총 23 페이지) - 파일 다운로드 YSS932 데이타시트 다운로드

No Preview Available !

YSS932
AC3D3B
96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP
OUTLINE
YSS932 is one chip LSI consisting of three built-in blocks : SPDIF receiver (DIR), Dolby Digital (AC-3) /
Pro Logic II & DTS decoder (Main DSP) and programmable sound fields processing DSP (Sub DSP).
The Sub DSP is capable of realizing various sound fields, such as virtual surround by down-loading the
program and coefficient from outside.
FEATURES
[ DIR Block ]
Sampling frequency: Two ranges are available including;
32k to 48kHz (normal rate) and 64k to 96kHz (double rate).
Provides master clock, 256fs, to DAC, ADC and the other peripheral devices. The clock output can be
controlled with various modes determined by register settings.
Has a pin that indicates the double rate operation.
Every channel status and user data can be read through the microprocessor interface.
Has an output pin for interrupt that is activated by changing of the status information.
Internal operation frequency: 25MHz
[ Main DSP Block ]
Dolby Digital (AC-3) / Pro Logic II and DTS decode.
High quality internal 24 bit DSP.
No external memory is required. (Memory for the center and surround channel signal delay is included.)
AC-3 Karaoke mode.
Supports compression mode at AC-3 / DTS decoding.
Included de-emphasis filter for the PCM signal.
Pro Logic II decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM signal.
Reads Dolby Digital / DTS decode information through the microprocessor interface.
Internal operation frequency: 30MHz
YAMAHA CORPORATION
www.DataSheet4U.com
YSS932 CATALOG
CATALOG No.: LSI-4SS932A2
2003.2

No Preview Available !

YSS932
[ Sub DSP Block ]
Capable of realizing various sound fields, such as simulation surround, output configuration and virtual
surround by downloading the programs from the microprocessor.
Adoption of the 32 bit floating-point DSP assuring highly accurate processing.
Up to 2.73 seconds delay at fs=48kHz achievable by adding DRAM or SRAM externally.
Internal operation frequency: 30MHz
[ Other Features ]
Connectable to almost all ADC and DAC by making appropriate settings to the control register.
Total of 16 general purpose input/output ports are provided.
2 built-in PLL circuits for generation of operation clocks for DIR block and DSP blocks.
Power supply voltage: 2 power sources (2.5V for core logic section and 3.3V for I/O section)
Si-gate CMOS process
128SQFP (YSS932-S)
Note:
"AC-3" and "Pro Logic II" are registered trademarks of Dolby Laboratories Licensing corporation.
"DTS" is a registered trademark of DTS, Inc.
Use of this LSI must be licensed by both Dolby Laboratories Licensing Corporation and DTS, Inc.
2

No Preview Available !

YSS932
BLOCK DIAGRAM
DIRPCO
DIRPRO
DIRSDO
SDIA
SURENC
KARAOKE
MUTE
CRC
AC3DATA
DTSDATA
NONPCM
ZEROFLG
XI
XO
CPO
SDOA0
SDOA1
SDOA2
SDIB0
SDIB1
SDIB2
SDIB3
VMOD BSMOD
DBL
PLL
Clock for DIR
Block (25MHz)
DIRO Interface
765
DDINSEL
DIR
IPORT5-7
UMOD CMOD
CRC
SDIASEL
SDIA Interface
PLL
Clock for DSP
Block (30MHz)
MainDSP
(AC-3/ProLogicII/DTS decoder)
SDOA Interface
C,LFE
LS,RS
L,R
SDIACKSEL
SDIBSEL
RAMD0-15
CASN
RASN
RAMWEN
RAMOEN
RAMA0-17
OVFB/END
SDIB Interface
OVFB
END
SubDSP
Coefficient /
Program RAM
SDOB Interface
DIRMCK
DIRBCK
DIRWCK
SDBCKI0
SDWCKI0
/SDBCKO
IPORT0-4
/CS
SO
SI
SCK
OPORT0-7
3