YSS932.pdf 데이터시트 (총 23 페이지) - 파일 다운로드 YSS932 데이타시트 다운로드

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YSS932
AC3D3B
96kHz DIR + Dolby Digital / Pro Logic II / DTS decoder + Sub DSP
OUTLINE
YSS932 is one chip LSI consisting of three built-in blocks : SPDIF receiver (DIR), Dolby Digital (AC-3) /
Pro Logic II & DTS decoder (Main DSP) and programmable sound fields processing DSP (Sub DSP).
The Sub DSP is capable of realizing various sound fields, such as virtual surround by down-loading the
program and coefficient from outside.
FEATURES
[ DIR Block ]
Sampling frequency: Two ranges are available including;
32k to 48kHz (normal rate) and 64k to 96kHz (double rate).
Provides master clock, 256fs, to DAC, ADC and the other peripheral devices. The clock output can be
controlled with various modes determined by register settings.
Has a pin that indicates the double rate operation.
Every channel status and user data can be read through the microprocessor interface.
Has an output pin for interrupt that is activated by changing of the status information.
Internal operation frequency: 25MHz
[ Main DSP Block ]
Dolby Digital (AC-3) / Pro Logic II and DTS decode.
High quality internal 24 bit DSP.
No external memory is required. (Memory for the center and surround channel signal delay is included.)
AC-3 Karaoke mode.
Supports compression mode at AC-3 / DTS decoding.
Included de-emphasis filter for the PCM signal.
Pro Logic II decoding for Dolby Digital 2 channels decoded signal as well as ordinary PCM signal.
Reads Dolby Digital / DTS decode information through the microprocessor interface.
Internal operation frequency: 30MHz
YAMAHA CORPORATION
www.DataSheet4U.com
YSS932 CATALOG
CATALOG No.: LSI-4SS932A2
2003.2

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YSS932
[ Sub DSP Block ]
Capable of realizing various sound fields, such as simulation surround, output configuration and virtual
surround by downloading the programs from the microprocessor.
Adoption of the 32 bit floating-point DSP assuring highly accurate processing.
Up to 2.73 seconds delay at fs=48kHz achievable by adding DRAM or SRAM externally.
Internal operation frequency: 30MHz
[ Other Features ]
Connectable to almost all ADC and DAC by making appropriate settings to the control register.
Total of 16 general purpose input/output ports are provided.
2 built-in PLL circuits for generation of operation clocks for DIR block and DSP blocks.
Power supply voltage: 2 power sources (2.5V for core logic section and 3.3V for I/O section)
Si-gate CMOS process
128SQFP (YSS932-S)
Note:
"AC-3" and "Pro Logic II" are registered trademarks of Dolby Laboratories Licensing corporation.
"DTS" is a registered trademark of DTS, Inc.
Use of this LSI must be licensed by both Dolby Laboratories Licensing Corporation and DTS, Inc.
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YSS932
BLOCK DIAGRAM
DIRPCO
DIRPRO
DIRSDO
SDIA
SURENC
KARAOKE
MUTE
CRC
AC3DATA
DTSDATA
NONPCM
ZEROFLG
XI
XO
CPO
SDOA0
SDOA1
SDOA2
SDIB0
SDIB1
SDIB2
SDIB3
VMOD BSMOD
DBL
PLL
Clock for DIR
Block (25MHz)
DIRO Interface
765
DDINSEL
DIR
IPORT5-7
UMOD CMOD
CRC
SDIASEL
SDIA Interface
PLL
Clock for DSP
Block (30MHz)
MainDSP
(AC-3/ProLogicII/DTS decoder)
SDOA Interface
C,LFE
LS,RS
L,R
SDIACKSEL
SDIBSEL
RAMD0-15
CASN
RASN
RAMWEN
RAMOEN
RAMA0-17
OVFB/END
SDIB Interface
OVFB
END
SubDSP
Coefficient /
Program RAM
SDOB Interface
DIRMCK
DIRBCK
DIRWCK
SDBCKI0
SDWCKI0
/SDBCKO
IPORT0-4
/CS
SO
SI
SCK
OPORT0-7
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PIN CONFIGRATION
YSS932
TESTXI
TESTXO
VDD2
XO
XI
TESTMS
TESTXEN
IPORT0
IPORT1
IPORT2
IPORT3
IPORT4
DDIN0
DDIN1
DDIN2
DDIN3
VSS
CPO
AVDD
DIRPCO
DIRPRO
AVSS
TESTBRK
TESTR1
TESTR2
VDD1
SDWCKI0
SDBCKI0
/SDBCKO
SDIA
SDOA2
SDOA1
SDOA0
SDIB3
SDIB2
SDIB1
SDIB0
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102 VSS
101 RAMA11
100 RAMA10
99 RAMA9
98 RAMA3
97 RAMA4
96 RAMA2
95 RAMA5
94 RAMA1
93 RAMA6
92 RAMA0
91 RAMA7
90 RAMA8
89 VDD1
88 VSS
87 RASN
86 RAMOEN
85 RAMWEN
84 CASN
83 RAMD15
82 RAMD14
81 RAMD13
80 RAMD12
79 RAMD11
78 RAMD10
77 RAMD9
76 RAMD8
75 VDD1
74 VSS
73 RAMD7
72 RAMD6
71 RAMD5
70 RAMD4
69 RAMD3
68 RAMD2
67 RAMD1
66 RAMD0
65 VDD2
< 128SQFP TOP VIEW >
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YSS932
PIN FUNCTION
No. Name I/O
Function
1 TESTXI I LSI Test pin (must be connected to VSS)
2 TESTXO O LSI Test pin (to be open)
3 VDD2
- +2.5V power supply (for internal core logic)
4 XO
O Crystal oscillator connection
5 XI
I Crystal oscillator connection (24.576MHz)
6 TESTMS I+ LSI Test pin (to be open)
7 TESTXEN I+ LSI Test pin (to be open)
8 IPORT0 I+ General purpose input port
9 IPORT1 I+ General purpose input port
10 IPORT2 I+ General purpose input port
11 IPORT3 I+ General purpose input port
12 IPORT4 I+ General purpose input port
13 DDIN0 Is DIR: Digital audio interface data input 0
14 DDIN1 Is DIR: Digital audio interface data input 1 / General purpose input port
15 DDIN2 Is DIR: Digital audio interface data input 2 / General purpose input port
16 DDIN3 Is DIR: Digital audio interface data input 3 / General purpose input port
17 VSS
- Ground
18 CPO
A PLL filter connection
19 AVDD
- +3.3V power supply (for DIR block)
20 DIRPCO A DIR: PLL filter connection
21 DIRPRO A DIR: PLL filter connection
22 AVSS
- Ground (for DIR block)
23 TESTBRK I+ LSI Test pin (to be open)
24 TESTR1 I+ Initial Clear input for PLL in DSP block
25 TESTR2 I+ LSI Test pin (to be open)
26 VDD1
- +3.3V power supply (for I/O)
27 SDWCKI0 I+ Word clock input for SDIA, SDOA, SDIB, SDOB
28 SDBCKI0 I+ Bit clock input for SDIA, SDOA, SDIB, SDOB
29 /SDBCKO O Reverse clock output of DIRBCK or SDBCKI0
30 SDIA
I Input of bitstream or PCM data to Main DSP
31 SDOA2 O PCM data output from Main DSP (C, LFE)
32 SDOA1 O PCM data output from Main DSP (LS, RS)
33 SDOA0 O PCM data output from Main DSP (L, R)
34 SDIB3 I+ PCM data input 3 to Sub DSP
35 SDIB2 I+ PCM data input 2 to Sub DSP
36 SDIB1 I+ PCM data input 1 to Sub DSP
37 SDIB0 I+ PCM data input 0 to Sub DSP
38 VSS
- Ground
39 VDD2
- +2.5V power supply (for internal core logic)
40 DIRSDO O Output of bitstream or PCM data from DIR
41 DIRWCK O DIR: Serial data word clock (fs) output
42 DIRBCK O DIR: Serial data bit clock (64fs) output
43 DIRMCK O DIR: Serial data master clock (256fs or 128fs) output
44 ERR/BS O DIR: Data error detect / Block start output
45 SYNC/U O DIR: Serial data synchronized timing / User data output
46 FS128/C O DIR: Serial data master clock 128fs / Channel status output
47 DBL/V O DIR: Double rate lock detect / Validity flag output
48 SDWCKI1 I+ Word clock input for SDIB, SDOB
49 SDBCKI1 I+ Bit clock input for SDIB, SDOB
50 VSS
- Ground
51 SDOB3 O PCM data output from Sub DSP
52 SDOB2 O PCM data output from Sub DSP
53 SDOB1 O PCM data output from Sub DSP
54 SDOB0 O PCM data output from Sub DSP
55 VDD1
- +3.3v power supply (for I/O)
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