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8-Bit, 500 MSPS,
1.8 V Analog-to-Digital Converter
AD9484
FEATURES
SNR = 47 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 7.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 79 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
Integrated input buffer
Excellent linearity
DNL = ±0.1 LSB typical
INL = ±0.1 LSB typical
LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required
Low power dissipation
670 mW at 500 MSPS—LVDS SDR output
Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Low cost digital oscilloscopes
Satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The AD9484 is an 8-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The part operates at up to a 500 MSPS conver-
sion rate and is optimized for outstanding dynamic performance
in wideband carrier and broadband systems. All necessary
functions, including a sample-and-hold and voltage reference,
are included on the chip to provide a complete signal conversion
solution. The VREF pin can be used to monitor the internal
reference or provide an external voltage reference (external
reference mode must be enabled through the SPI port).
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
LVDS (ANSI-644) compatible and support twos complement,
offset binary format, or Gray code. A data clock output is available
for proper output data timing.
FUNCTIONAL BLOCK DIAGRAM
VREF PWDN
AGND
AVDD
CML
VIN+
VIN–
CLK+
CLK–
REFERENCE
AD9484
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC 8
CORE
SERIAL PORT
OUTPUT 8
STAGING
LVDS
SCLK/DFS SDIO CSB
Figure 1.
DRVDD
DRGND
D7± TO D0±
OR+
OR–
DCO+
DCO–
Fabricated on an advanced BiCMOS process, the AD9484 is availa-
ble in a 56-lead LFCSP, and is specified over the industrial
temperature range (−40°C to +85°C). This product is protected
by a U.S. patent.
PRODUCT HIGHLIGHTS
1. High Performance.
Maintains 47 dBFS SNR at 500 MSPS with a 250 MHz input.
2. Ease of Use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 1.8 V supply simplifies system power supply design.
3. Serial Port Control.
Standard serial port interface supports various product
functions, such as data formatting, power-down, gain
adjust, and output test pattern generation.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.

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AD9484
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
DC Specifications ......................................................................... 3 
AC Specifications.......................................................................... 4 
Digital Specifications ................................................................... 5 
Switching Specifications .............................................................. 6 
Absolute Maximum Ratings............................................................ 7 
Thermal Resistance ...................................................................... 7 
ESD Caution.................................................................................. 7 
Pin Configuration and Function Descriptions............................. 8 
Typical Performance Characteristics ........................................... 10 
Equivalent Circuits ......................................................................... 13 
REVISION HISTORY
6/11—Rev. 0 to Rev. A
Change to General Description Section ........................................ 1
Change to Aperture Time Parameter in Table 4........................... 6
Change to Figure 34 ....................................................................... 16
Changes to Register 17 and Register 18 in Table 12 .................. 20
3/11—Revision 0: Initial Version
Theory of Operation ...................................................................... 14 
Analog Input and Voltage Reference ....................................... 14 
Clock Input Considerations...................................................... 15 
Power Dissipation and Power-Down Mode ........................... 16 
Digital Outputs ........................................................................... 16 
Timing ......................................................................................... 17 
VREF............................................................................................ 17 
AD9484 Configuration Using the SPI ..................................... 18 
Hardware Interface..................................................................... 18 
Configuration Without the SPI ................................................ 18 
Memory Map .................................................................................. 20 
Reading the Memory Map Table.............................................. 20 
Reserved Locations .................................................................... 20 
Default Values ............................................................................. 20 
Logic Levels................................................................................. 20 
Outline Dimensions ....................................................................... 23 
Ordering Guide .......................................................................... 23 
Rev. A | Page 2 of 24

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AD9484
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
INTERNAL REFERENCE
VREF
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
POWER SUPPLY
AVDD
DRVDD
Supply Currents
IAVDD 3
IDRVDD3/SDR Mode4
Power Dissipation
SDR Mode4
Standby Mode
Power-Down Mode
Temp
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
−3.0
−5.0
−0.25
−0.15
0.71
1.18
1.75
1.75
Typ Max
8
Guaranteed
0
+3.0
1.0
+7.0
±0.13
+0.25
±0.1
+0.15
0.75 0.78
18
0.07
1.5 1.6
1.7
1
1.3
1.8 1.9
1.8 1.9
283 300
89 100
670 720
40 50
2.5 7
Unit
Bits
mV
mV
% FS
% FS
LSB
LSB
LSB
LSB
V
μV/°C
%/°C
V p-p
V
pF
V
V
mA
mA
mW
mW
mW
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at a rated sample rate.
4 Single data rate mode; this is the default mode of the AD9484.
Rev. A | Page 3 of 24

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AD9484
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 2.
Parameter1, 2
SNR
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
SINAD
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
WORST HARMONIC (SECOND or THIRD)
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
SFDR
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD)
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
TWO-TONE IMD
fIN1 = 119.5 MHz, fIN2 = 122.5 MHz
ANALOG INPUT BANDWIDTH
Full Power
Temp
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Min
46.5
46.4
75
Typ Max Unit
47.0 dBFS
47.0 dBFS
47.0 dBFS
dBFS
47.0 dBFS
46.9 dBFS
47.0 dBFS
47.0 dBFS
47.0 dBFS
dBFS
47.0 dBFS
46.9 dBFS
7.5 Bits
7.5 Bits
7.5 Bits
7.5 Bits
7.5 Bits
−87 dBc
−86 dBc
−87 dBc
−75 dBc
83 dBc
70 dBc
82 dBc
81 dBc
82 dBc
dBc
79 dBc
70 dBc
−82 dBc
−81 dBc
−82 dBc
−75 dBc
79 dBc
77 dBc
−77 dBc
1 GHz
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. A | Page 4 of 24

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AD9484
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
High Level Input (VIH)
Low Level Input (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (SDIO, CSB)
Logic 0 Input Current (SDIO, CSB)
Logic 1 Input Current (SCLK, PDWN)
Logic 0 Input Current (SCLK, PDWN)
Input Capacitance
LOGIC OUTPUTS2
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min Typ Max
CMOS/LVDS/LVPECL
0.9
0.2 1.8
−1.8 −0.2
−10 +10
−10 +10
8 10 12
4
0.8 × DRVDD
0.2 × DRVDD
0
−60
50
0
4
247
1.125
454
1.375
Unit
V
V p-p
V p-p
μA
μA
pF
V
V
μA
μA
μA
μA
pF
mV
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 LVDS RTERMINATION = 100 Ω.
Rev. A | Page 5 of 24