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11 mW Power, 2.3 V to 5.5 V,
Complete DDS
AD9838
FEATURES
2.3 V to 5.5 V power supply
MCLK speed: 16 MHz (B grade), 5 MHz (A grade)
Output frequency up to 8 MHz
Sinusoidal and triangular outputs
On-board comparator
3-wire SPI interface
Extended temperature range: −40°C to +125°C
Power-down option
11 mW power consumption at 2.3 V
20-lead LFCSP
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect detection
Test and medical equipment
GENERAL DESCRIPTION
The AD9838 is a low power DDS device capable of producing high
performance sine and triangular outputs. It also has an on-board
comparator that allows a square wave to be produced for clock
generation. Consuming only 11 mW of power at 2.3 V, the
AD9838 is an ideal candidate for power-sensitive applications.
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits wide: with a 16 MHz
clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz
clock rate, the AD9838 can be tuned to 0.02 Hz resolution.
Frequency and phase modulation are configured by loading
registers through the serial interface and by toggling the registers
using software or the FSELECT and PSELECT pins, respectively.
The AD9838 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V. The
analog and digital sections are independent and can be run from
different power supplies; for example, AVDD can equal 5 V with
DVDD equal to 3 V.
The AD9838 has a power-down pin (SLEEP) that allows external
control of the power-down mode. Sections of the device that are
not being used can be powered down to minimize current con-
sumption. For example, the DAC can be powered down when
a clock output is being generated.
The AD9838 is available in a 20-lead LFCSP_WQ package.
AVDD AGND DGND
FUNCTIONAL BLOCK DIAGRAM
DVDD CAP/2.5V
REFOUT FSADJUST
MCLK
FSELECT
28-BIT FREQ0
REG
28-BIT FREQ1
REG
REGULATOR
VCC
2.5V
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
MUX
PHASE
ACCUMULATOR
(28-BIT)
12
Σ
SIN
ROM
MUX
10-BIT
DAC
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
MUX
DIVIDE
BY 2
MSB
COMP
IOUT
IOUTB
16-BIT CONTROL
REGISTER
MUX
SIGN BIT OUT
SERIAL INTERFACE
AND
CONTROL LOGIC
COMPARATOR
VIN
AD9838
FSYNC SCLK SDATA
PSELECT
SLEEP RESET
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.

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AD9838
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Timing Characteristics ................................................................ 5 
Absolute Maximum Ratings............................................................ 6 
Thermal Resistance ...................................................................... 6 
ESD Caution.................................................................................. 6 
Pin Configuration and Function Descriptions............................. 7 
Typical Performance Characteristics ............................................. 9 
Test Circuit ...................................................................................... 12 
Terminology .................................................................................... 13 
Theory of Operation ...................................................................... 14 
Circuit Description......................................................................... 15 
Numerically Controlled Oscillator Plus Phase Modulator ... 15 
SIN ROM ..................................................................................... 15 
Digital-to-Analog Converter (DAC) ....................................... 15 
Comparator ................................................................................. 15 
Regulator...................................................................................... 16 
REVISION HISTORY
4/11—Rev. 0 to Rev. A
Change to Title.................................................................................. 1
Change to Figure 3 ........................................................................... 5
Change to Figure 8 ........................................................................... 9
4/11—Revision 0: Initial Version
Functional Description.................................................................. 17 
Serial Interface ............................................................................ 17 
Latency Period ............................................................................ 17 
Control Register ......................................................................... 17 
Frequency and Phase Registers ................................................ 19 
Reset Function ............................................................................ 20 
Sleep Function ............................................................................ 20 
SIGN BIT OUT Pin.................................................................... 21 
IOUT and IOUTB Pins ............................................................. 21 
Powering Up the AD9838 ......................................................... 21 
Applications Information .............................................................. 24 
Grounding and Layout .............................................................. 24 
Interfacing to Microprocessors................................................. 24 
Evaluation Board ............................................................................ 26 
System Demonstration Platform.............................................. 26 
AD9838 to SPORT Interface..................................................... 26 
Evaluation Kit ............................................................................. 26 
Crystal Oscillator vs. External Clock....................................... 26 
Power Supply............................................................................... 26 
Evaluation Board Schematics ................................................... 27 
Evaluation Board Layout........................................................... 29 
Outline Dimensions ....................................................................... 30 
Ordering Guide .......................................................................... 30 
Rev. A | Page 2 of 32

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AD9838
SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ, RLOAD = 200 Ω for IOUT and IOUTB, unless
otherwise noted.
Table 1.
Parameter1
Min Typ Max Unit Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10 Bits
Update Rate
A Grade
5 MSPS
B Grade
16 MSPS
IOUT Full Scale2
3.0 mA
VOUT Maximum
0.6 V
VOUT Minimum
Output Compliance3
30 mV
0.8 V
DC Accuracy
Integral Nonlinearity (INL)
±1 LSB
Differential Nonlinearity (DNL)
±0.5 LSB
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio (SNR)
A Grade
−63 dB fMCLK = 5 MHz, fOUT = fMCLK/4096
B Grade
−64 dB fMCLK = 16 MHz, fOUT = fMCLK/4096
Total Harmonic Distortion (THD)
A Grade
−64 dBc fMCLK = 5 MHz, fOUT = fMCLK/4096
B Grade
−64 dBc fMCLK = 16 MHz, fOUT = fMCLK/4096
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
A Grade
−68 dBc fMCLK = 5 MHz, fOUT = fMCLK/50
B Grade
−66 dBc fMCLK = 16 MHz, fOUT = fMCLK/50
Narrow-Band (±200 kHz)
A Grade
−97 dBc fMCLK = 5 MHz, fOUT = fMCLK/50
B Grade
−92 dBc fMCLK = 16 MHz, fOUT = fMCLK/50
Clock Feedthrough
A Grade
−68 dBc fMCLK = 5 MHz, fOUT = reset
B Grade
−65 dBc fMCLK = 16 MHz, fOUT = reset
Wake-Up Time
1 ms
COMPARATOR
Input Voltage Range
1
V p-p
AC-coupled internally
Input Capacitance
10 pF
Input High-Pass Cutoff Frequency
3
MHz
Input DC Resistance
5 MΩ
Input Leakage Current
10 μA
OUTPUT BUFFER
Output Rise/Fall Time
12 ns Using a 15 pF load
Output Jitter
120
ps rms
3 MHz sine wave 0.6 V p-p
VOLTAGE REFERENCE
Internal Reference
1.11 1.18 1.24 V
REFOUT Output Impedance4
1 kΩ
Reference TC
100 ppm/°C
FSADJUST Voltage
1.14 V
Rev. A | Page 3 of 32

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AD9838
Parameter1
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
POWER SUPPLIES
AVDD
DVDD
IAA 5
IDD5
A Grade
B Grade
IAA + IDD5
A Grade
B Grade
Low Power Sleep Mode
A Grade
B Grade
Min Typ Max Unit
1.7
2.0
2.8
3
V
V
V
0.6 V
0.7 V
0.8 V
10 μA
pF
2.3 5.5 V
2.3 5.5 V
3.7 5
mA
0.9 2
mA
1.2 2.4 mA
4.6 7
mA
4.9 7.4 mA
0.4 mA
0.4 mA
1 Operating temperature range is −40°C to +125°C; typical specifications are at 25°C.
2 For compliance with the specified load of 200 Ω, IOUT full scale should not exceed 4 mA.
3 Guaranteed by design.
4 Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
5 Measured with the digital inputs static and equal to 0 V or DVDD.
Test Conditions/Comments
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
fMCLK = 16 MHz, fOUT = fMCLK/4096
IDD code dependent; see Figure 7
See Figure 6
DAC powered down; see Table 17
Rev. A | Page 4 of 32

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TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t11A
t12
Limit at TMIN to TMAX
200/62.5
80/26
80/26
25
10
10
5
10
t4 − 5
5
3
8
8
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Description
MCLK period (5 MHz/16 MHz)
MCLK high duration (5 MHz/16 MHz)
MCLK low duration (5 MHz/16 MHz)
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
SCLK falling edge to FSYNC rising edge time
Data setup time
Data hold time
FSELECT, PSELECT setup time before MCLK rising edge
FSELECT, PSELECT setup time after MCLK rising edge
SCLK high to FSYNC falling edge setup time
1 Guaranteed by design; not production tested.
Timing Diagrams
MCLK
t1
t2
t3
Figure 2. Master Clock
AD9838
MCLK
FSELECT,
PSELECT
VALID DATA
t11
VALID DATA
t11A
VALID DATA
Figure 3. Control Timing
SCLK
FSYNC
t12
SDATA
t5
t7 t6
t4
t8
D15 D14
t10
t9
D2 D1
D0
Figure 4. Serial Timing
D15 D14
Rev. A | Page 5 of 32