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Q32M210
Precision Mixed-Signal
32-bit Microcontroller
Introduction
Q32M210 is a precision, mixedsignal 32bit microcontroller. The
microcontroller is built on the high performance ARM® CortextM3
processor.
The microcontroller incorporates a highly configurable sensor
interface designed to work directly with a wide range of sensors
having multiple characteristics, including specialized electrochemical
sensors. The sensor interface includes dual programmable gain
amplifiers, dual 16bit AnalogtoDigital converters, triple 10bit
DigitaltoAnalog converters (for voltage waveform generation and
other applications) and three uncommitted, lownoise opamps with
configurable signal multiplexing. Flexible connectivity to external
nonvolatile memory, personal computers, wireless devices, LCD
displays and a wide range of other peripherals is enabled by several
digital interfaces including I2C, USB (2.0 fullspeed compliant) and a
highspeed SPI/SQI interface.
The microcontroller features flexible clocking options as well as
intelligent failure monitoring of power and application interruptions
required by high performance, portable, battery operated applications.
All necessary clocks including an internal oscillator, realtime clock
and a dedicated clock for USB operation are available onchip
(external crystals required for RTC and USB).
An embedded power management unit, which incorporates several
low power modes, allows application developers to minimize both
standby and active power under a wide range of operating conditions.
The ultralow sleep current makes the microcontroller ideal for
applications that remain inactive for long periods of time.
A large onchip nonvolatile flash memory (256 kB) combined
with onchip SRAM (48 kB) supports complex applications and
simplifies application development. The flash contains builtin
hardware error checking and correction (ECC) for application
reliability. Additionally, a configurable DMA unit which supports
independent peripheraltomemory, memorytomemory, and
memorytoperipheral channels provides flexible, low power data
transfers without processor intervention.
A suite of industrystandard development tools, handson training
and full technical support are available to reduce design cycle time and
speed timetomarket.
The Q32M210 Microcontroller is PbFree, Halogen Free/BFR Free
and RoHS Compliant
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TLLGA140
DUALROW
CASE 513AL
MARKING DIAGRAM
Q32M210
AWLYYWWG
Q32M210 = Device Code
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 50 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
April, 2011 Rev. 5
1
Publication Order Number:
Q32M210/D

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Q32M210
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definition and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ESD and Latchup Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Detailed Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Example Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Key Features
Ultra LowPower and Smart Power Management
Less than 400 mA / MHz, up to 16 MHz clock speed
Reliable operation down to 1.8 V; 3.3 V nominal supply
voltage
Ultralowcurrent sleep mode with Realtime Clock
active (< 750 nA)
Lowcurrent standby mode with register and SRAM
retention (< 26 mA)
Integrated power supplies minimize need for external
components. Only a minimum of external passives is
required
Efficient, Powerful and Robust Processing
Architecture
32bit ARM CortexM3 CPU
256 kB onchip flash with integrated hardware ECC for
program and user data storage
48 kB onchip SRAM
Flexible DMA, 4 generalpurpose timers, CRC
calculator
No external voltage required for flash write operation
LowNoise, LowLeakage, LowTemperature Drift,
Configurable Sensor Interface
Triple ultra lownoise opamps with lowleakage inputs
and configurable outputs
Dual onchip Programmable Gain Amplifiers (PGA)
and ADCs with flexible input multiplexing and wide
dynamic range
Reconfigurable voltage detection unit
Optimal dynamic range scaling of sensor signals
Flexible onchip signal routing for dynamic
reconfigurability
Minimal temperature drift of gain and offset errors
allows for precise calibration
Builtin Temperature Sensor
Predictable Operation
Dedicated brownout protection circuit prevents
execution of code outside of operating range
Integrated hardwarebased ECC for onchip flash
maintains code and data integrity
Watchdog timer
High Precision AnalogtoDigital Conversion and
DigitaltoAnalog Conversion
Dual 16bit ADCs with onthefly data rate
configurability
Triple 10bit DACs with configurable dynamic range
Precision Voltage Reference
Onchip, low temperature drift (< 50 ppm/°C) voltage
reference for ADCs and DACs
Flexible OnChip Clocking
Processor supports speeds up to 16 MHz provided
either through internal oscillator or externally supplied
clock
Flexible Sensor Interconnections
Triple low Ron analog multiplexers, including an 8:1
input mux
Quad SPST and quad multiswitches for effective
simultaneous connection to different sensors
USB 2.0 FullSpeed Interface
Builtin transceiver for 2.0 Fullspeed compatible
(12 Mbps) operation with dedicated power supply
Flexible External Interfaes
Configurable Interface Wakeup pins with configurable
pullups and pulldowns
8 Configurable GPIO interrupts
Dual UARTs, dual SPI, SQI, I2C, PCM (including I2S
mode), GPIOs
LCD Interface
Up to 112 segments with integrated charge pump and
backlight driver (up to 10 mA)
Packaging
Available in 140pin TLLGA
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DAC[2:0]
AUX_IN[2:0]
AAF[1:0]
SPST0_[A,B]
SPST1_[A,B]
SPST2_[A,B]
SPST3_[A,B]
MSW0_[A,B,C]
MSW1_[A,B,C]
MSW2_[A,B,C]
MSW3_[A,B,C]
NMI
VBAT
VBATA
VDDD
VADC
VREF
IREF
VCP
CP0,1
VDBL
VDDUSB
VDDIO0
VDDIO1
VLCD0
VLCD1
VLCD
ILV
RSTB
VSS
USBXTAL0
USBXTAL1
RTCXTAL0
RTCXTAL1
EXT_CLK
ALT[1:0]
A0_IN[7:0]
A0_IN, A0_REF,
A0_OUT[A,B]
A1_IN, A1_REF,
A1_OUT[A,B]
A2_IN, A2_REF,
A2_OUT[A,B]
JTDI
JTDO
JTMS
JTCK
JRSTB
DAC[2:0]
Temperature
Sensor
ADC
PGA Input
Multiplexer[1:0]
PGA[1:0]
ADC[1:0]
Switches
SPST Switches
MultiSwitches
PWM Control
PMU
Regulators
Wakeup
Controller
Power
Supervisor
POR
PORD
Clocks
Internal
Oscillator
RTC Oscillator
USB Oscillator
Clock
Distribution
Opamps
Opamp[2:0]
Multiplexers
(8:1, ALT0,
ALT1)
JTAG
Debug Port
Q32M210
Peripheral Bus
DMA
DMA Control
Registers
System
Memory
Memory
Arbiter
System Bus
NVIC
Private
Peripheral
Bus
SYSTICK
ARM
CortexM3
Instruction Bus
Data
Bus
Memory Arbiter
Program
Memory
ROM
Flash
CoEnCtroCller
Flash
CoWntrrioteller
RTC
Timer x 4
Watchdog Timer
CRC
Figure 1. Functional Overview
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IF0
SPI0 (SQI)
GPIO x 4
USRCLK x 3
IF1
SPI1
GPIO x 4
PCM
IF2
UART0
GPIO x 2
IF3
UART1
GPIO x 2
SQI (IO[3:2])
IF4
GPIO x 32
LCD Driver
PWM x 4
IF5
GPIO x 4
Wakeup x 4
I2C
USB
PHY
USB controller
USB memory
IF0.[3:0]
IF1.[3:0]
IF2.[1:0]
IF3.[1:0]
IF4.[31:0]
IF5.[3:0]
SCL
SDA
USBDN
USBDP

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Q32M210
FUNCTIONAL OVERVIEW
Operating Modes
Three lowpower operating modes are available
1. Run mode – used during normal program
execution; the entire device is fully operational in
run mode
2. Standby mode – used for lower current
consumption, with paused program execution and
fast wakeup
3. Sleep mode – used for ultra low current
consumption, with no program execution and
restart after wakeup
Each mode is designed to provide the lowest possible
current consumption, while maintaining power to specific
parts of the device.
Run Mode
Run mode provides a low power mode where the entire
system is fully functional. In run mode, the device enables
the onchip VDDD Digital Supply Regulator to provide
power to the ARM CortexM3 Processor. The processor is
clocked from either an internal or an external clock source.
The program can be executed from the internal flash or
SRAM.
The application can selectively enable or disable sensor
interface components, including supply regulators and
references, as required. The application may also adjust the
device clock frequency through the internal oscillator or
through clock divisors to minimize power consumption. The
digital and analog interfaces may be configured as required
in run mode. Internal clock dividers provide all the
necessary clocks to the sensor interface and peripherals.
While in run mode, the application may switch into either
sleep mode or standby mode.
Standby Mode
Standby mode provides a low power mode where the
digital system state is retained. In standby mode, the ARM
CortexM3 Processor execution is paused. The VDDD
Digital Supply Regulator voltage is reduced. The contents of
all the registers and SRAM are retained.
The power supervisor automatically disables and powers
down the sensor interface components, including the analog
supply regulators and references. The application may
selectively enable or disable the RTC, RTC alarm, and the
Wakeup controller. The internal oscillator is automatically
disabled.
When in standby mode, the device may be switched into
run mode by either the RTC alarm or by up to four external
events (through the Wakeup controller).
Sleep Mode
Sleep mode provides an ultralow power mode where the
system is waiting for a wakeup event. In sleep mode, the
power supervisor automatically disables and powers down
the digital and analog supply regulators, the internal
oscillator, and all the sensor interface components. The
application may selectively enable or disable the RTC, RTC
alarm, and the Wakeup controller.
When in sleep mode, the device may be switched into run
mode by either the RTC alarm or by up to four external
events (through the Wakeup controller). After exiting sleep
mode, the system state is reset and execution starts from the
beginning of the ROM program.
A general purpose retention register is available to store
state. The retention register contents are retained after
exiting sleep mode. This register may be used by the
application to quickly restore its state.
Power Supply
The device can powered from a single battery supply such
as a 2032 lithium coin cell. The device supplies all required
regulated voltages and references onchip. This allows the
device to operate directly from a single battery supply
without the need for external regulators or switches.
VBAT and VBATA
The main power supply input for the device is VBAT. The
supplied voltage to VBAT is typically 3.3 V but it can be
supplied with any voltage between 1.8 V and 3.6 V. The
device will operate reliably across this entire power supply
range. This flexibility allows for a wide range of battery
types to be directly connected to the device.
The sensor interface power supply for the device is
VBATA. VBATA is typically 3.3 V but it can be supplied
with any voltage between 1.8 V and 3.6 V. The sensor
interface will operate reliably across this entire power
supply range however the performance of the sensor
interface may be reduced when VBATA drops below 2.2 V.
VBATA also powers the IF5 pins.
In a typical application, VBATA and VBAT are both
connected directly to the battery supply. To increase the
useful operating life of the battery VBATA may be
externally connected to the onchip charge pump output
(VDBL) instead of the battery. In this configuration the
sensor interface power supply remains nominally 3.5 V
even as the battery voltage drops.
VBAT is monitored by the builtin power supervisor.
VBATA is not directly monitored but may be measured
through the sensor interface.
Regulators
All required voltages for normal device operation are
generated onchip.
VDDD
The VDDD Digital Supply Regulator (VDDD) provides
a nominal 1.8 V power supply for the ARM CortexM3
Processor, digital peripheral and memories, including the
onchip flash. VDDD is generated onchip and is connected
to the digital components internally. It is also available
externally. Flash memory reads and writes require only a
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Q32M210
minimum voltage of 1.8 V. No external power management
circuitry is required to support flash access.
VADC
The VADC Analog Supply Regulator (VADC) provides a
nominal 1.8 V power supply for the ADCs and PGAs. This
separate supply ensures noise immunity between the analog
and digital subsystems. VADC may be enabled or disabled
as required to save power.
VDBL
The VDBL Charge Pump (VDBL) provides a nominal
3.5 V power supply under any normal operating range
battery voltage. VDBL is powered from the dedicated
onchip Charge Pump Supply Regulator (VCP). This
separate supply ensures noise immunity between VDBL, the
other onchip power supplies as well as from the battery.
VDBL is normally used to power an LCD segment display
and associated backlight or any other external devices
requiring a fixed, high voltage rail. VDBL may also be used
to power the sensor interface. This is useful when a fixed,
higher voltage rail is required for the sensor interface
compared to the battery voltage.
ILV
An onchip programmable current sink (ILV) is available
to adjust the amount of current from VDBL through an LED
backlight. In a typical configuration an LED is connected
between VDBL and ILV. The application controls the LED
brightness by adjusting the current setting.
VREF Precision Voltage Reference
The device provides an onchip lowtemperature drift
reference voltage, VREF. VREF is factory calibrated to 0.9 V.
VREF is available externally and is also connected internally
to the ADCs and DACs for their reference voltages.
I/O Pin Supplies
The device’s I/O pins are powered from multiple supplies.
This allows the device to match its I/O voltage levels to
external devices as required.
One bank of digital I/O pins is powered from VDDIO0.
The voltage applied to VDDIO0 determines the logic level
for the associated pins. A second bank of mixed signal I/O
pins is powered from VDDIO1.
The voltage applied to VDDIO1 determines the digital
logic level for the associated pin. When the mixed signal I/O
pins are configured for LCD operation, VDDIO1 must be at
or above VLCD supply voltage for proper operation.
The USB pins USBDP and USBDN are powered directly
from VDDUSB.
The IF5 pins are powered directly from VBATA.
All analog signal pins are powered directly from VBATA.
Power Supervisor, Poweron Reset, and BrownOut
Protection
The device contains a dedicated hardware power
supervisor for monitoring the supply voltages. The power
supervisor ensures the device operates deterministically,
and without any unexpected behavior during all supply
conditions.
The power supervisor releases the internal Poweron
Reset (POR) when the supply voltage on VBAT exceeds the
minimum threshold for proper operation. The release of
POR enables the VDDD Digital Supply Regulator. The
power supervisor continues to monitor VBAT. If VBAT
drops below the minimum threshold for proper operation the
device is reset.
No external circuitry is required for proper device startup.
All required startup delays and reset thresholds are
generated onchip. The RSTB pin may be left floating
during startup.
The ARM CortexM3 Processor and all digital subsystem
components including the flash, SRAM, and peripherals
will operate reliability down to a nominal VDDD supply
voltage of 1.8 V. In run mode, the power supervisor
continually monitors VDDD. If VDDD drops below the
minimum threshold for proper operation the device is reset.
The power supervisor is automatically disabled in sleep
mode and standby mode to save power.
Supply Monitor
During run mode, the actual voltage levels for VBAT,
VBATA, VREF, and VADC can be measured through either
one of the ADC channels. This allows the application to
determine the actual supply levels and appropriately handle
the graceful shutdown of the system when the battery
approaches its useful endoflife. Additional voltages may
be monitored through one of the auxiliary inputs.
In a system configuration where the sensor interface may
be supplied from either the battery or the VDBL Charge
Pump, the application can use the measured VBAT voltage
level to determine whether to enable VDBL or continue to
supply the sensor interface from the battery.
External Reset
The device contains an external reset pin (RSTB). When
RSTB is asserted, the digital subsystem including the ARM
CortexM3 Processor is reset. The realtime clock counters
are not reset by an external reset. The RSTB function is only
available in run mode. Asserting the RSTB pin during the
Poweron Reset sequence will prevent the ARM
CortexM3 Processor from running. The system will be held
in reset until the pin is released. RSTB can be left floating.
System Wakeup
Wakeup occurs when the device is switched from standby
mode or sleep mode into run mode. This can be
accomplished through one of the wakeup mechanisms. The
wakeup controller allows for up to four external events to
wake up the system. Two IF5 pins (IF5.0, IF5.1) will wakeup
the system when a HightoLow transition is detected. Two
IF5 pins (IF5.2, IF5.3) will wakeup the system when a Low
toHigh transition is detected. The RTC Alarm can also be
configured to wakeup the system at a predetermined time.
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