minimum voltage of 1.8 V. No external power management
circuitry is required to support flash access.
The VADC Analog Supply Regulator (VADC) provides a
nominal 1.8 V power supply for the ADCs and PGAs. This
separate supply ensures noise immunity between the analog
and digital subsystems. VADC may be enabled or disabled
as required to save power.
The VDBL Charge Pump (VDBL) provides a nominal
3.5 V power supply under any normal operating range
battery voltage. VDBL is powered from the dedicated
on−chip Charge Pump Supply Regulator (VCP). This
separate supply ensures noise immunity between VDBL, the
other on−chip power supplies as well as from the battery.
VDBL is normally used to power an LCD segment display
and associated backlight or any other external devices
requiring a fixed, high voltage rail. VDBL may also be used
to power the sensor interface. This is useful when a fixed,
higher voltage rail is required for the sensor interface
compared to the battery voltage.
An on−chip programmable current sink (ILV) is available
to adjust the amount of current from VDBL through an LED
backlight. In a typical configuration an LED is connected
between VDBL and ILV. The application controls the LED
brightness by adjusting the current setting.
VREF Precision Voltage Reference
The device provides an on−chip low−temperature drift
reference voltage, VREF. VREF is factory calibrated to 0.9 V.
VREF is available externally and is also connected internally
to the ADCs and DACs for their reference voltages.
I/O Pin Supplies
The device’s I/O pins are powered from multiple supplies.
This allows the device to match its I/O voltage levels to
external devices as required.
One bank of digital I/O pins is powered from VDDIO0.
The voltage applied to VDDIO0 determines the logic level
for the associated pins. A second bank of mixed signal I/O
pins is powered from VDDIO1.
The voltage applied to VDDIO1 determines the digital
logic level for the associated pin. When the mixed signal I/O
pins are configured for LCD operation, VDDIO1 must be at
or above VLCD supply voltage for proper operation.
The USB pins USBDP and USBDN are powered directly
The IF5 pins are powered directly from VBATA.
All analog signal pins are powered directly from VBATA.
Power Supervisor, Power−on Reset, and Brown−Out
The device contains a dedicated hardware power
supervisor for monitoring the supply voltages. The power
supervisor ensures the device operates deterministically,
and without any unexpected behavior during all supply
The power supervisor releases the internal Power−on
Reset (POR) when the supply voltage on VBAT exceeds the
minimum threshold for proper operation. The release of
POR enables the VDDD Digital Supply Regulator. The
power supervisor continues to monitor VBAT. If VBAT
drops below the minimum threshold for proper operation the
device is reset.
No external circuitry is required for proper device startup.
All required start−up delays and reset thresholds are
generated on−chip. The RSTB pin may be left floating
The ARM Cortex−M3 Processor and all digital subsystem
components including the flash, SRAM, and peripherals
will operate reliability down to a nominal VDDD supply
voltage of 1.8 V. In run mode, the power supervisor
continually monitors VDDD. If VDDD drops below the
minimum threshold for proper operation the device is reset.
The power supervisor is automatically disabled in sleep
mode and standby mode to save power.
During run mode, the actual voltage levels for VBAT,
VBATA, VREF, and VADC can be measured through either
one of the ADC channels. This allows the application to
determine the actual supply levels and appropriately handle
the graceful shutdown of the system when the battery
approaches its useful end−of−life. Additional voltages may
be monitored through one of the auxiliary inputs.
In a system configuration where the sensor interface may
be supplied from either the battery or the VDBL Charge
Pump, the application can use the measured VBAT voltage
level to determine whether to enable VDBL or continue to
supply the sensor interface from the battery.
The device contains an external reset pin (RSTB). When
RSTB is asserted, the digital subsystem including the ARM
Cortex−M3 Processor is reset. The real−time clock counters
are not reset by an external reset. The RSTB function is only
available in run mode. Asserting the RSTB pin during the
Power−on Reset sequence will prevent the ARM
Cortex−M3 Processor from running. The system will be held
in reset until the pin is released. RSTB can be left floating.
Wakeup occurs when the device is switched from standby
mode or sleep mode into run mode. This can be
accomplished through one of the wakeup mechanisms. The
wakeup controller allows for up to four external events to
wake up the system. Two IF5 pins (IF5.0, IF5.1) will wakeup
the system when a High−to−Low transition is detected. Two
IF5 pins (IF5.2, IF5.3) will wakeup the system when a Low−
to−High transition is detected. The RTC Alarm can also be
configured to wakeup the system at a predetermined time.