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8-Input NAND Gate
TECHNICAL DATA
KK74HCT30A
The KK74HCT30A is high-speed Si-gate CMOS device and is pin
compatible with low power Schottky TTL (LSTTL) . The device provide
the 8-input NAND function.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
KK74HCT30AN Plastic
KK74HCT30AD
SOIC
TA = -55° ÷ 125° C for all packages
LOGIC DIAGRAM
A PIN ASSIGNMENT
B
A1
14 V CC
C
B2
13 -
D
C3
12 H
Y
D4
11 G
E
E5
10 -.
F
F6
9-
G
GND 7
8Y
H
FUNCTION TABLE
PIN 14 =VCC
PIN 7 = GND
Inputs
Output
ABСDE FGH
Y
LXXXXXXX
H
XLXXXXXX
H
XXLXXXXX
H
XXXLXXXX
H
XXXXLXXX
H
XXXXXLXX
H
XXXXXXLX
H
XXXXXXXL
H
HHHHHHHH
L
X = don’t care
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KK74HCT30A
MAXIMUM RATINGS*
Symbol
VCC
VIN
VOUT
IIN
IOUT
ICC
PD
Tstg
TL
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP**
SOIC Package**
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
±25
±50
750
500
-65 to +150
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mA
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
TA
tr, tf
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min Max Unit
4.5 5.5
V
0 VCC V
-55 +125 °C
0 1000 ns
0 500
0 400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or
VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
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KK74HCT30A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VIH Minimum High-Level VOUT0.1V or
Input Voltage
VOUT VCC-0.1V
IOUT⎢≤ 20 µA
VIL Maximum Low -Level VOUT0.1V or
Input Voltage
VOUT VCC-0.1V
IOUT⎢≤ 20 µA
VOH Minimum High-Level VIN=VIH or VIL
Output Voltage
IOUT⎢ ≤ - 20 µA
VIN= VIH or VIL
IOUT⎢ ≤ - 4.0 mA
VOL Maximum Low-Level VIN= VIH or VIL
Output Voltage
IOUT⎢ ≤ 20 µA
VIN= VIH or VIL
IOUT⎢ ≤ 4.0 mA
IIL Maximum Low-Level VIN= 0 V
Input Leakage Current
IIH Maximum High-Level VIN= VCC
Input Leakage Current
ICC Maximum Quiescent VIN=VCC or 0 V
Supply Current
IOUT=0 µA
(per Package)
ICCT
Maximum
Additional Quiescent
VIN=2.4V any one input,
VIN=0 V or VCC, others
Supply Current
inputs
IOUT=0 µA
VCC Guaranteed Limit Unit
V 25 °C 85 125
to °C °C
-55°C
4.5 2.0 2.0 2.0 V
5.5 2.0 2.0 2.0
4.5 0.8 0.8 0.8 V
5.5 0.8 0.8 0.8
4.5 4.4 4.4 4.4 V
5.5 5.4 5.4 5.4
4.5 3.98 3.84 3.70
4.5 0.1 0.1 0.1
5.5 0.1 0.1 0.1
4.5 0.26 0.33 0.4
V
5.5 -0.1 -1.0 -1.0 µA
5.5 0.1 1.0 1.0 µA
5.5 2.0 20 40 µA
5.5 -55°C 25°C ÷ mА
-125°C
2.9 2.4
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KK74HCT30A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
tPHL, tPLH
tTHL, tTLH
Maximum Propagation Delay (Figure 1)
Maximum Output Transition Time
(Figure 1)
VCC Guaranteed Limit
V 25 °C 85°C 125°C
to
-55°C
4.5 41 52 63
4.5 15 19 22
CIN Maximum Input Capacitance
5.0 10 10 10
Unit
ns
ns
pF
Power Dissipation Capacitance (Per Gate)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
TA=25°C,VCC=5.0 V
27
Input
Output
tf
0.9
V2
0.1
tPLH
tr
0.9
V2
0.1
tPHL
V1
GND
0.9
V2
0.1
tTLH
0.9
V2
0.1
tTHL
VCC
0V
pF
V1 = 3 V
V2 = 1.3 V
Figure 1. Switching Waveforms
PULSE
GENERATOR
VI
VCC
DEVICE
UNDER
RT TEST
VO
CL
50 pF
Termination resistance RT – should
be equal to ZOUT of pulse generators
Figure 2. Test Circuit
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N SUFFIX PLASTIC DIP
(MS - 001AA)
A
14
1
8
B
7
FL
C
-T- SEATING
N PLANE
G
KM
D
H
NOTES:
0.25 (0.010) M T
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
KK74HCT30A
Symbol
A
B
C
D
F
G
H
J
K
L
M
N
Dimension, mm
MIN
18.67
MAX
19.69
6.1 7.11
5.33
0.36 0.56
1.14 1.78
2.54
7.62
0° 10°
2.92 3.81
7.62 8.26
0.2 0.36
0.38
D SUFFIX SOIC
(MS - 012AB)
A
14
8
H BP
1G
7
C
R x 45
-T-
D
NOTES:
K
0.25 (0.010) M T C M
SEATING
PLANE
J
F
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B 0.25 mm (0.010) per side.
Symbol
A
B
C
D
F
G
H
MJ
K
M
P
R
Dimension, mm
MIN MAX
8.55 8.75
3.8 4
1.35 1.75
0.33 0.51
0.4 1.27
1.27
5.27
0° 8°
0.1 0.25
0.19 0.25
5.8 6.2
0.25 0.5
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