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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F32G08CBABA, MT29F64G08C[E/F]ABA, MT29F128G08C[J/K/M]ABA,
MT29F256G08CUABA, MT29F32G08CBABB, MT29F32G08CBCBB,
MT29F64G08CFABB, MT29F64G08CECBB, MT29F128G08CJABB,
MT29F128G08C[K/M]CBB, MT29F256G08CUCBB
Features
Open NAND Flash Interface (ONFI) 2.1-compliant1
Multiple-level cell (MLC) technology
Organization
Page size x8: 4320 bytes (4096 + 224 bytes)
Block size: 256 pages (1024K + 56K bytes)
Plane size: 2 planes x 2048 blocks per plane
Device size: 32Gb: 4096 blocks;
64Gb: 8192 blocks;
128Gb: 16,384 blocks;
256Gb: 32,768 blocks
Synchronous I/O performance
Up to synchronous timing mode 4
Clock rate: 12ns (DDR)
Read/write throughput per pin: 166 MT/s
Asynchronous I/O performance
Up to asynchronous timing mode 4
tRC/tWC: 25ns (MIN)
Array performance
Read page: 50µs (MAX)
Program page: 900µs (TYP)
Erase block: 3ms (TYP)
Operating Voltage Range
VCC: 2.7–3.6V
VCCQ: 1.7–1.95V, 2.7–3.6V
Command set: ONFI NAND Flash Protocol
Advanced Command Set
Program cache
Read cache sequential
Read cache random
One-time programmable (OTP) mode
Multi-plane commands
Multi-LUN operations
Read unique ID
Copyback
First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 108).
RESET (FFh) required as first command after power-
on
Operation status byte provides software method for
detecting
Operation completion
Pass/fail condition
Write-protect status
Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
Copyback operations supported within the plane
from which data is read
Quality and reliability
Data retention: 10 years
Endurance: 5000 PROGRAM/ERASE cycles
Operating temperature:
Commercial: 0°C to +70°C
Industrial (IT): –40ºC to +85ºC
Package
52-pad LGA
48-pin TSOP
100-ball BGA
Note: 1. The ONFI 2.1 specification is available at
www.onfi.org.
PDF: 09005aef836c9ded
Rev. F 12/09 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 32G 08 C B A B A WP
Micron Technology
NAND Flash
29F = NAND Flash memory
Density
32G = 32Gb
64G = 64Gb
128G = 128Gb
256G = 256Gb
Device Width
08 = 8 bits
Level
Bit/Cell
C 2-bit
Classification
Die # of CE# # of R/B# I/O
B1
1
1 Common
E2
2
2 Separate
F2
2
2 Common
J4
2
2 Common
K4
2
2 Separate
M4
4
4 Separate
U8
4
4 Separate
Operating Voltage Range
A = VCC: 3.3V (2.7–3.6V), VCCQ: 3.3V (2.7–3.6V)
C = VCC: 3.3V (2.7–3.6V), VCCQ: 1.8V (1.7–1.95V)
Note: 1. Pb-free package.
ES :B
Design Revision
B = Second revision
Production Status
Blank = Production
ES = Engineering sample
Reserved for Future Use
Blank
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade (synchronous mode only)
-12 = 166 MT/s
Package Code
C5 = 52-pad VLGA 14mm x 18mm x 1.0mm1
H1 = 100-ball VBGA 12mm x 18mm x 1.0mm1
H2 = 100-ball TBGA 12mm x 18mm x 1.2mm1
H3 = 100-ball LBGA 12mm x 18mm x 1.4mm1
WP = 48-pin TSOP1 (CPL)
Interface
A = Async only
B = Sync/Async
Generation Feature Set
B = Second set of device features
PDF: 09005aef836c9ded
Rev. F 12/09 EN
2 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.

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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ...................................................................................................................................... 14
Architecture ................................................................................................................................................... 19
Device and Array Organization ....................................................................................................................... 20
Bus Operation – Asynchronous Interface ........................................................................................................ 27
Asynchronous Enable/Standby ................................................................................................................... 27
Asynchronous Bus Idle ............................................................................................................................... 27
Asynchronous Commands .......................................................................................................................... 28
Asynchronous Addresses ............................................................................................................................ 29
Asynchronous Data Input ........................................................................................................................... 30
Asynchronous Data Output ........................................................................................................................ 31
Write Protect .............................................................................................................................................. 32
Ready/Busy# .............................................................................................................................................. 32
Bus Operation – Synchronous Interface ........................................................................................................... 37
Synchronous Enable/Standby ..................................................................................................................... 38
Synchronous Bus Idle/Driving .................................................................................................................... 38
Synchronous Commands ........................................................................................................................... 39
Synchronous Addresses .............................................................................................................................. 40
Synchronous DDR Data Input ..................................................................................................................... 41
Synchronous DDR Data Output .................................................................................................................. 42
Write Protect .............................................................................................................................................. 44
Ready/Busy# .............................................................................................................................................. 44
Device Initialization ....................................................................................................................................... 45
Activating Interfaces ....................................................................................................................................... 46
Activating the Asynchronous Interface ........................................................................................................ 46
Activating the Synchronous Interface .......................................................................................................... 46
Command Definitions .................................................................................................................................... 48
Reset Operations ............................................................................................................................................ 50
RESET (FFh) ............................................................................................................................................... 50
SYNCHRONOUS RESET (FCh) .................................................................................................................... 51
Identification Operations ................................................................................................................................ 52
READ ID (90h) ............................................................................................................................................ 52
READ ID Parameter Tables ............................................................................................................................. 53
Configuration Operations ............................................................................................................................... 54
SET FEATURES (EFh) ................................................................................................................................. 54
GET FEATURES (EEh) ................................................................................................................................. 55
READ PARAMETER PAGE (ECh) ...................................................................................................................... 59
Parameter Page Data Structure Tables ............................................................................................................. 60
READ UNIQUE ID (EDh) ................................................................................................................................ 71
Status Operations ........................................................................................................................................... 72
READ STATUS (70h) ................................................................................................................................... 73
READ STATUS ENHANCED (78h) ............................................................................................................... 74
Column Address Operations ........................................................................................................................... 75
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 75
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 76
CHANGE WRITE COLUMN (85h) ................................................................................................................ 77
CHANGE ROW ADDRESS (85h) ................................................................................................................... 78
Read Operations ............................................................................................................................................. 80
PDF: 09005aef836c9ded
Rev. F 12/09 EN
3 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.

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32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
READ MODE (00h) ..................................................................................................................................... 82
READ PAGE (00h-30h) ................................................................................................................................ 83
READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 84
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 85
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 87
READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 88
Program Operations ....................................................................................................................................... 90
PROGRAM PAGE (80h-10h) ........................................................................................................................ 90
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 92
PROGRAM PAGE MULTI-PLANE 80h-11h ................................................................................................... 94
Erase Operations ............................................................................................................................................ 96
ERASE BLOCK (60h-D0h) ............................................................................................................................ 96
ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 97
Copyback Operations ..................................................................................................................................... 98
COPYBACK READ (00h-35h) ....................................................................................................................... 99
COPYBACK PROGRAM (85h–10h) .............................................................................................................. 100
COPYBACK READ MULTI-PLANE (00h-32h) .............................................................................................. 100
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 101
One-Time Programmable (OTP) Operations ................................................................................................... 102
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 103
PROTECT OTP AREA (80h-10h) .................................................................................................................. 104
READ OTP PAGE (00h-30h) ........................................................................................................................ 105
Multi-Plane Operations ................................................................................................................................. 106
Multi-Plane Addressing ............................................................................................................................. 106
Interleaved Die (Multi-LUN) Operations ........................................................................................................ 107
Error Management ........................................................................................................................................ 108
Output Drive Impedance ............................................................................................................................... 109
AC Overshoot/Undershoot Specifications ...................................................................................................... 112
Synchronous Input Slew Rate ........................................................................................................................ 113
Output Slew Rate ........................................................................................................................................... 114
Electrical Specifications ................................................................................................................................. 115
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 117
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) .................................. 118
Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 118
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 119
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 121
Electrical Specifications – Array Characteristics .............................................................................................. 124
Asynchronous Interface Timing Diagrams ...................................................................................................... 125
Synchronous Interface Timing Diagrams ........................................................................................................ 136
Revision History ............................................................................................................................................ 158
Rev. F, Production – 12/09 ......................................................................................................................... 158
Rev. E – 8/09 .............................................................................................................................................. 158
Rev. D – 2/09 ............................................................................................................................................. 158
Rev. C – 1/09 ............................................................................................................................................. 158
Rev. B – 12/08 ............................................................................................................................................ 159
Rev. A – 11/08 ............................................................................................................................................ 160
PDF: 09005aef836c9ded
Rev. F 12/09 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.

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32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 26
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 27
Table 4: Synchronous Interface Mode Selection ............................................................................................. 37
Table 5: Command Set .................................................................................................................................. 48
Table 6: Read ID Parameters for Address 00h ................................................................................................. 53
Table 7: Read ID Parameters for Address 20h .................................................................................................. 53
Table 8: Feature Address Definitions .............................................................................................................. 54
Table 9: Feature Address 01h: Timing Mode ................................................................................................... 56
Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 56
Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 57
Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 57
Table 13: Parameter Page Data Structure ....................................................................................................... 60
Table 14: Status Register Definition ............................................................................................................... 72
Table 15: OTP Area Details ........................................................................................................................... 103
Table 16: Error Management Details ............................................................................................................. 108
Table 17: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 109
Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 109
Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 110
Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 110
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 111
Table 22: Overshoot/Undershoot Parameters ................................................................................................ 112
Table 23: Test Conditions for Input Slew Rate ................................................................................................ 113
Table 24: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 113
Table 25: Input Slew Rate (VCCQ= 2.7–3.6V) ................................................................................................... 113
Table 26: Test Conditions for Output Slew Rate ............................................................................................. 114
Table 27: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 114
Table 28: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 114
Table 29: Absolute Maximum Ratings by Device ............................................................................................ 115
Table 30: Recommended Operating Conditions ............................................................................................ 115
Table 31: Valid Blocks per LUN ..................................................................................................................... 115
Table 32: Capacitance: 100-Ball BGA Package ................................................................................................ 116
Table 33: Capacitance: 48-Pin TSOP Package ................................................................................................ 116
Table 34: Capacitance: 52-Pad LGA Package .................................................................................................. 116
Table 35: Test Conditions ............................................................................................................................. 117
Table 36: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 117
Table 37: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 118
Table 38: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 118
Table 39: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 119
Table 40: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 119
Table 41: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 121
Table 42: Array Characteristics ..................................................................................................................... 124
PDF: 09005aef836c9ded
Rev. F 12/09 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.