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Ordering number : ENA1499
LV56081GP
Bi-CMOS LSI
For CCD
Charge Pump Power Supply
Overview
The LV56081GP is charge pump power supply for CCD.
Functions
The charge pump boosts the +3.3V input by multiplying with +6, then by -3 to regulate the voltage to the specified level.
The output voltage is +15V, -5.5V necessary for CCD.
Soft start function incorporated, which reduces the inrush current at start of charge pump.
Short-circuit protection function incorporated.
Four types of operating frequency selectable.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VDD max
Pd max
Topr
Tstg
Conditions
with specified substrate *1
*1 : Specified substrate : 40mm × 50mm × 0.8mm, glass epoxy board
Ratings
3.5
0.8
-20 to +80
-40 to +125
Unit
V
W
°C
°C
Allowable Operating Ratings at Ta = 25°C, PGND = 0V
Parameter
Symbol
Conditions
Supply voltage
Input CLK frequency
VDD
CKIN
SEL=H *2
Input High voltage
Input Low voltage
VINH
VINL
EN pin
EN pin
*2 : Note that the charge pump frequency should be adjusted with S0/S1 so that it becomes 2MHz or less.
min
3.0
0.1
0.7VDD
-0.1
Ratings
typ
3.3
max
3.45
8
VDD
0.4
Unit
V
MHz
V
V
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
61009 MS 20061207-S00003 No.A1499-1/7
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LV56081GP
Electrical Characteristics at Ta = 25°C, VDD = 3.3V, SGND = 0V, PGND = 0V,IH=20mA, IL=5mA, S0=H, S1=L,
Unless otherwise specified
Parameter
Circuit current dissipation
VH output load current
VL output load current
Reference voltage
Output voltage accuracy
Symbol
IDD1
IDD2
IH ave
IL ave
VREF
VH
Conditions
EN = L
EN = H no load
VDD = 3.0V
VDD = 3.0V
VDD = 3.0 to 3.45V, design guarantee
Ta = -20°C to +80°C, design guarantee
Ratings
min typ
15
17
-8
1.239
14.55
1.305
15
max
30
25
20
1.37
15.35
Unit
µA
mA
mA
mA
V
V
V
VL
-5.65
-5.5
-5.25
V
Output voltage at OFF
VH holding time
Protection circuit masking time
VH load regulation
VL load regulation
Input pin current
VH monitoring voltage
VOFF
Toff
Tmask
VH
VL
Iin
VTvlon
After capacitive discharge
VLoff VHoff
Load 1mA 20mA
Load 0.5mA 8mA
Pins EN, S0, S1, SEL and CLK
-50 0 +50 mV
5 ms
18 ms
30 mV
50 mV
12.6
17.5
22.5 µA
8V
Power efficiency
Peff CP+Regulator (VH+VL)
70 %
Inrush current
Irush
600 mA
Oscillation frequency
f clk
Note : The design specification items are design guarantees and are not measured.
1.5 2 2.5 MHz
Package Dimensions
unit : mm (typ)
3322A
TOP VIEW
3.5
SIDE VIEW
BOTTOM VIEW
(0.125)
(C0.17)
SIDE VIEW
0.25
24
21
0.5 (0.5)
SANYO : VCT24(3.5X3.5)
Pd max -- Ta
1.0
Specified board: 40×50×0.8mm3
glass epoxy board.
0.8
0.6
0.4
0.36
0.2
0
-20 0
20 40 60 80 100
Ambient temperature, Ta -- °C
No.A1499-2/7
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Pin Assignment
LV56081GP
24 23 22 21 20 19
S0 1
18 VM C13
S1 2
17 C12A
EN 3
16 C11A
SGND 4
15 PVDD
SVDD 5
14 C12B
CLK 6
13 PGND
7 8 9 10 11 12
Top view
Pin Function
Pin No.
Name
1 S0
2 S1
3 EN
4 SGND
5 SVDD
6 CLK
7 SEL
8 VH C23
9 VH C22
10 C21A
11 NC
12 C11B
13 PGND
14 C12B
15 PVDD
16 C11A
17 C12A
18 VM C13
19 C31B
20 PGND1
21 C31A
22 VL C32
23 VL C33
24 TEST
Mode
Charge pump frequency changeover pin
Charge pump frequency changeover pin
System enable pin (Hi active)
Small signal system GND pin
Small signal system VDD pin
External CLK input pin
CLK selector pin (L: built-in CLK, H: external CLK)
VH (+15V) regulator output pin
Boost voltage output (+6VDD)
Boost capacitor connection pin (on the load transfer side)
Boost capacitor connection pin (driver side)
+3-fold boost power GND pin
Boost capacitor connection pin (driver side)
Power system VDD pin
Boost capacitor connection pin (load transfer side)
Boost capacitor connection pin (load transfer side)
Boost voltage output (+3VDD)
+2-fold and -1-fold boost capacitor connection pin (driver side)
+2-fold and -1-fold boost power GND pin
-1-fold boost capacitor connection pin (load transfer side)
Boost voltage output (-3VDD)
VL (-5.5V) regulator output pin
Test pin (OPEN or GND short-circuited)
No.A1499-3/7
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Block Diagram
VDD
3.3V
15
PVDD
SVDD 5
1µF
/VDD
4
PGND
20
PGND1
LV56081GP
10µF
/VDD
TSD
bandgap
voltage
reference
+3 times
step up
circuit
+3VDD
PGND
13
14 C12B
C11B
12
1µF
/VDD
1µF
/2VDD
16 C11A
17 C12A 2.2µF
18 /3VDD
VM C13
To A
0.22µF
/3VDD
C31B
19
21
C31A
-1 times
step up
circuit
1µF
/3VDD VL C32
22
-3VDD
VL C33
23
1µF
VL=-7.5V
VL Reg
EN 3
TEST 24
timing
generator
+2 times
step up
circuit
+6VDD
A
1µF
10 /3VDD
C21A
2.2µF
VH C22 /6VDD
9
sequence
generator
VH Reg
2bitMUX
2MHz
oscillator
divider
MUX
6
CLK
2.2µF
8
VH C23
VH=+15V
1 S0
2 S1
7 SEL
Lo : internal CLK
Hi : external CLK
No.A1499-4/7
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LV56081GP
Short-circuit Protection
VH and VL output pins incorporate the short-circuit protection function.
When the output pins are short-circuited to allow the large current to flow, IC is latched OFF to interrupt output.
To reset from the interrupted state, set the EN pin to L, then reset it again to H.
Frequency Selection
The charge pump operating frequency can be changed with S0 and S1
logics.
For light load, the reactive load can be reduced by lowering the
operating frequency.
SEL logic also enables synchronous operation with external CLK.
The charge pump is operated with the frequency equivalent to 1/2 of
input CLK.
(The IC internal oscillator is used for the sequence, so that it is
normally ON regardless of SEL.
S0 S1
LL
HL
LH
HH
CP operating frequency
SEL=L
SEL=H
1MHz
1/2 CLK
500kHz
250kHz
1/4 CLK
1/8 CLK
125kHz
1/16 CLK
For minimum 9.4ms after startup with the EN signal set to H, the IC
internal clock is used to operate the charge pump with 1 MHz regardless
of the input of SEL, S0, and S1 pins. After the 9.4ms(min) period, the
charge pump frequency is changed over according to the state of SEL,
S0, and S1 pins. The changeover frequency is set as shown in the table
right.
SEL
L IC internal oscillator
H Synchronous operation with external CLK
Internal Equivalent Circuit
S0 pin
S1 pin
SEL pin
CLK pin
DQ
Q
Internal
1MHz
VH regulator start
signal
L H in 9.4ms (min) after EN = H
B DQ
Y
A
Q
2-input multiplexer
Truth Table
SEL Y
LA
HB
clk
clk/2
clk/4
clk/8
Y
Charge pump
clock
4-input multiplexer
DQ
DQ
Q Q Truth Table
S0 S1 Y
L L clk
H L clk/2
L H clk/4
H H clk/8
External signal input pin
Internal signal
No.A1499-5/7
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