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,. ANALOG s -<:-<- I17t:J700 '8' G v- H-V 9'&::sO
85 MHzDirect
W DEVICES
DigitaSl ynthesizer
FEATURES
100 MHz Typical/8S MHz Minimum Clock Rate
32-Bit Phase Accumulator
12-Bit Sine Output
>90 dB Spurious Free Dynamic Range
Continuous Frequency Update
On-Board Data Ready Signal
APPLICATIONS
Frequency Synthesizers
DDS Tuning
Digital Demodulation
FM Modulators
AD9955
I
GENERAL DESCRIPTION
The AD99SS is a 100 MHz direct digital synthesizer for fre-
quency synthesis applications. It comprises a 32-bit phase accu-
mulator and a IS-bit phase-to-12-bit sine amplitude converter.
The control logic is CMOS compatible, and the clock input is
TTL. CMOS outputs are latched on board, and a data ready
signal is provided.
Designed for applications in communications, instrumentation,
and military systems, the AD99SS can be combined with a clock
reference and a DAC such as the AD97l3B or AD9721 to form
a digitally-controlled analog frequency reference.
The AD99SS is available in an SO-leadplastic quad flatpack
(PQFP) for commercial (O°Cto + 70°C) temperature range appli-
cations. Contact the factory for information concerning the avail-
ability of a military temperature range device.
PSEl
BREN
F[O:31)
COUT
FUNCTIONAL BLOCK DIAGRAM
RSTO
TCMS
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BRCLK
FCLD
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DATA
READY
REV.0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329.4700
Fax: 617/326-8703
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AD9955- SPECIFICATIONS
ELECTRICALCHARACTERISTIC(+SVs = +5 V;fClK= 40MHzC; l = 20pF,unlessotherwisenoted)
irest AJ>9955
Parameter (Conditions)
iremperature
Level Min iryp Max
CMOS INPUTS 1
Logic "I" Voltage
Logic "0" Voltage
Logic "I" Current
Logic "0" Current
InpUt Capacitance
Full
Full
Full
Full
+ 25°C
II 3.5
II 1.5
II 1.0
II -1.0
V 10
CMOS OUTPUTS
Logic "1" Voltage (VIH)
Logic "0" Voltage (VIL)
Logic "1" Current
Logic "0" Current
OutpUt Capacitance
Full
Full
Full
Full
+25°C
II 4.5
II 0.4
II 12
II 12
V3
TTL INPUTS2
Logic "1" Voltage
Logic "0" Voltage
Logic "1" Current
Logic "0" Current
Input Capacitance
POWER SUPPLIES
+Vs Current3
CLK = 50 MHz
CLK = 100 MHz
Nominal Power Dissipation
CLK = 50 MHz
CLK = 100 MHz
Relative to Frequency
Full
Full
Full
Full
+ 25°C
Full
+ 25°C
+25°C
+ 25°C
+25°C
IV 2.0
II 0.8
II 1.0
II -1.0
V4
IV 120 160
V 240
V 600
V 1.2
V 11.5
AC SPECIFICA TIONS4
Clock Update Rate (CLK)5
Frequency Update Rate (BRCLK)6
Clock Pulse Width
CLK Digital "1"
CLK Digital "0"
Frequency Update Pulse Width
BRCLK Digital "1"
BRCLK Digital "0"
Input Rise/Fall Times
CLK Rise Time
CLK Fall Time
BRCLK Rise Time
BRCLK Fall Time
BRCLK Input Timing
Setup Time (tcs, tEsf
Hold Time (tcH, tEHf
CLK Input Timing
Setup Time (tLS)8
Hold Time (tLH)8
RESET 0 Timing
Setup Time (tRS)9
Hold Time (tRH)9
Output Timing Characteristics
Data Output Delay (tOD)lO
DRDY Output Delay (tDR)lO
Output Data Setup Time (tos)ll
Carry Output Delay12
Spurious-Free Dynamic Range (SFDR)
Worst Case Spur13
Latency of Initial Data14
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
+25°C
+ 25°C
+ 25°C
IV 85 100
II 40
IV 7.9 5.7
IV 3.8 2.2
II 10
II 10
IV
IV
IV
IV
2
2
5
5
II 5 2
IV 5 1.8
IV 2.0 0.7
IV 2.0 0.7
IV 6
IV 6
IV 3.4 6.1 8.7
IV 4.7 7.5 10
IV 0.8 1.9
V 7.7
V >90
V 14
Units
V
V
fJ.A
fJ.A
pF
V
V
mA
mA
pF
V
V
fJ.A
fJ.A
pF
mA
mA
mW
W
mW/MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
dBc
Clock Cycles
-2-
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AD9955
NOTES
'Includes F[0:31], PSEL, BREN, FCLD, CIN, TGLE, BRCLK, TCMS, and RSTO.
'Only the clock (CLK) is TTL compatible.
'focT = 1/2 fCLK' See performance curves.
.Nominal conditions (V'H = 3.4 V; V'L = 0.4 V).
'Based on minimum clock pulse width duty cycle (68% HIGH @ 85 MHz).
6This specification defines the maximum rate at which the output frequency tUning word (F[0:3I]) can be updated.
7Referenced to 2.5 V point of rising edge of BRCLK, specified for F[0:31], BREN.
"Referred to rising edge of CLK, specified for FCLD. CIN setup time is typically 1.2 ns, specified for FCLD, CIN.
"Referred to 1.6 V point of the rising edge of CLK. See Timing Diagram.
IOReferenced to 1.6 V point of the rising edge of CLK for 1.6 V point of the rising/falling edge of SIN [0:11]; or the falling edge of DRDY. Load is shown
below.
"Referenced from 1.6 V point of the rising/falling edge of SIN[O:II] to 1.6 V point of the falling edge of DATA READY. Specified driving AD9713B; no addi-
tional capacitive load.
"Referenced from 1.6 V point of rising edge of CLK to 1.6 V point of the rising/falling edge of COUTo
"Based on proprietary phase-to-sine algorithm, TGLE HIGH.
'.Referred to CLK for FCLD high. See Timing Diagram.
EXPLANATION OF TEST LEVELS
Test Level
I - 100% production tested.
II - 100% production tested at +25°e; parameter is
guaranteed by design and characterization at temp-
erature extremes.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
Parameters based on characterization testing have limits based on 6 sigma of
a normal distribution; typical values are the mean of the distribution.
ABSOLUTE MAXIMUM RATINGSI
Supply Voltage (+Vs)
-0.5 V to +7 V
Input Voltage. . . . . . . . . . . . . . . . . -0.5 V to +Vs +0.5 V
Output Voltage Swing. . . . . . . . . . . -0.5 V to +Vs +0.5 V
Operating Temperature Range (Ambient)
ooe to + 70oe
Maximum Junction Temperature2
+ 150oe
Storage Temperature Range. . . . . . . . . . . -65°e to + 150oe
Lead Temperature (soldering, 10 seconds) . . . . . . . . . + 250oe
ORDERING GUIDE
Model
AD9955KS-66t
AD9955KS-62
AD9955/PeB
Temperature
Range
ooe to + 70oe
ooe to + 70oe
N/A
Package
80-Terminal Plastic
Quad Flatpack
80-Terminal Plastic
Quad Flatpack
DDS Evaluation Board
NOTES
'Model AD9955KS-66 units are shipped in a standard JEDEC tray; mini-
mum order quantity is 66 units (I full tray).
'AD9955KS-6 units are shipped in a nonstandard tray; minimum order
quantity is 6 units (I full tray). Three nonstandard trays will fit in a stan-
dard JEDEC tray outline, allowing use with standard assembly equipment.
Contact factory for details.
NOTE: All units are dry packed to inhibit moistUre absorption. Units which
are exposed to air for more than 48 hours should be baked for 24 hours at
+ 125°C prior to assembly.
+5V AD97138
NOTES
'Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
'Typical thermal impedance; part soldered in place:
alA = 62°CIW
alC = 7°CIW.
1OkQ
AD9955 Load Circuit
REV.0
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AD9955
AD9955 PIN DESCRIPTIONS
Name
Description
GND
Ground Reference Voltage Connection.
+Vs
BRCLK
CLK
Positive voltage power connection, nominally + 5 V.
Buffer Register Clock. Data inputs are loaded into
the Frequency Control Word Buffer Register on the
rising edge of BRCLK when register is enabled
(BREN input at Logic "1").
System Clock. Continuous TTL signal for
synchronizing all internal operations, except loading
of Frequency Control Word Buffer Register; rising
edge initiates synchronization.
F[0:31] 32 parallel data inputs for loading frequency tuning
word.
BREN
Buffer Load Enable Signal. Enables loading of data
into the Frequency Control Word Buffer Register.
If BREN is logic "0," register retains its contents. If
BREN is Logic "1," theFrequency Control Word
Buffer Register either (1) parallel loads the data
present at F[0:31] inputs (PSEL = HIGH) or (2)
serially shifts data present at F[31] input (PSEL =
LOW).
FCLD Frequency Control Load Enable Signal. FCLD =
HIGH enables loading of data from Frequency
Control Word Buffer Register into Frequency
Control Register. Loading takes place on next rising
edge of CLK signal. FCLD = LOW disables
DRDY
loading of data.
Data Ready Signal. Output data (SIN [0: 11]) is
valid on the rising edge of DRDY, which tracks
propagation delay variations of the output data vs.
temperature. The duty cycle of DRDY is dependent
on the duty cycle of the CLK input. The DRDY
signal should be used only for applications which
have a very high clock rate (85 Msps) and require
operation over a wide temperature range. Normally
allowed to float.
CIN Carry-In signal is provided as the carry input to the
least significant bit (LSB) of the 32-bit adder in the
phase accumulator. This signal is used as the carry
TGLE
input only if the TGLE signal is a logic zero; carry
has 1 LSB weight, and is used for stacking units for
64-bit DDS. Normally tied to ground.
Carry Toggle Enable. When HIGH, the CIN signal
is disabled, and the Carry-In toggles internally
between HIGH and LOW on each clock (CLK)
cycle to reduce the worst case spurious response of
the digital output signal by 3.92 dB. Normally tied
to ground.
TCMS
Twos Complement/Magnitude Mode Select. Selects
binary output format of data on SIN[O:11] outputs.
If TCMS is a Logic "1," format of output data at
SIN[O:11] is in twos complement format. If TCMS
is a Logic "0," data is binary unsigned magnitude
format. Normally tied to ground.
SIN[O:11] 12 parallel data bits comprising the sine data output.
Frequency of the sine data outputs is defined by the
Name
RSTO
COUT
PSEL
Description
Frequency Control Register (~ phase) as
( )~ PhaSe
louT = !eLK ~
Binary data format of 12-bit samples is either twos
complement or unsigned magnitude, determined by
TCMS signal.
Reset Phase to Zero Signal. Activates synchronous
reset of the Phase Accumulation Register to a
binary value of "0," or zero radians. Reset is
enabled when RSTO is a Logic "1" and takes place
on rising edge of system clock (CLK). Normally
low.
Carry-Out signal output of the 32-bit adder in the
phase accumulator; used for stacking two AD9955
units for 64-bit DDS. Normally allowed to float.
ParalleUSerial Frequency Control Word Buffer
Input Selector. Selects mode for loading the Buffer
Register. If a load is enabled (BREN = "1"), and
PSEL is a Logic "1," data is parallel loaded into the
Frequency Control Word Buffer Register from the
FO:31] inputs on the next rising edge of BRCLK. If
a load is enabled and PSEL is a Logic "0," data is
serially shifted into the Frequency Control Word
Buffer Register from the F[31] input on rising edge of
BRCLK.
PIN DESIGNATIONS
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GND I'
,FO(MSB) I
AD9955
TOP VIEW
(NOIIO Scala)
F'6124
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-4- REV.0
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DIE INFORMATION
Die Dimensions. . . . . . . . . . . . .215 x 199 x 20.7 (:!: 1) mils
PadDimensions
4x4mils
Metalization
Aluminum
Backing
SubstratePotential
None
Ground
Passivation
Oxynitride
Die Attach
Bond Wire
Epoxy
Gold
AD9955
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AD9955 Chip Layout
FIXED
FREQUENCY
REFERENCE
GENERATES SAMPLES
OF A SINE WAVE
IJ
I - - - - D-;-GITc;AcLuli - - - -I
CONVERTS SINE
SAMPLES INTO
ANALOG SIGNAL
I
II PHASE
N
PHASE
ACCUMULATOR
\ ---------------
SPECIFIES OUTPUT
FREQUENCY AS
FRACTION OF CLOCK
FREQUENCY
.,,1111111111111111
SINE
AMPLITUDE
CONVERTER
~
DIGITAL.
TO.
ANALOG
CONVERTER
rv
fo
rv
Figure 1. Block Diagram of DDS Generator
DDS
Direct digital synthesis (DDS) is a method of deriving a wide-
band, digitally controlled frequency (sine wave) synthesizer from
a single reference frequency (system clock).
The circuit has three major components:
1. Phase accumulator
2. Phase-to-amplitude converter
3. Digital-to-analog converter
These major stages and their relationships to one another are
illustrated in the block diagram shown above.
The phase accumulator is a digital device which generates the
phase increment of the output waveform. Its input is a digital
word which (with the reference oscillator) determines the fre-
quency of the output waveform. The output of the phase accu-
mulator stage represents the current phase of the generated
waveform. In effect, the accumulator serves as a variable-
frequency oscillator generating a digital ramp. The frequency of
the signal is defined by .lphase as
.lphase
.lphase
four = .A..phaseMAXfCLOCK= --yr- !cLOCK
Translating phase information from the phase accumulator into
amplitude data takes place in the phase-to-amplitude converter.
This is most commonly accomplished by means of a look-up
table (LUT) stored in memory, but may be calculated instead
using a digital algorithm to minimize circuit complexity and/or
increase the update rate.
In the final step of frequency synthesis, amplitude data is con-
verted into an analog signal. This is done by a digital-to-analog
(D/ A) converter which must have good linearity; low glitch
impulse; and fast, symmetrical rise and fall times. When it does,
the frequency synthesizer is able to produce a spectrally pure
waveform.
REV. 0
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