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240pin DDR3 SDRAM Registered DIMM
DDR3L SDRAM Registered DIMM
Based on 2Gb A-die
HMT325R7AFR8A
HMT351R7AFR8A
HMT351R7AFR4A
HMT31GR7AFR8A
HMT31GR7AFR4A
HMT42GR7AMR4A
*Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 0.1 / Nov. 2009
1
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Revision History
Revision No.
0.1
History
Initial Release
Draft Date
Nov. 2009
Remark
Preliminary
Rev. 0.1 / Nov. 2009
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Description
Hynix Registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM DUal In-Line
Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM
devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems
such as servers and workstations.
Features
• Power Supply: VDD=1.35V (1.283V to 1.45V)
• VDDQ = 1.35V (1.283V to 1.45V)
• Backward Compatible with 1.5V DDR3 Memory Module
• VDDSPD=3.0V to 3.6V
• Functionality and operations comply with the DDR3L SDRAM datasheet
• 8 internal banks
• Data transfer rates: PC3L-10600, PC3L-8500
• Bi-Directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
• Supports ECC error correction and detection
• On-Die Termination (ODT)
• Temperature sensor with integrated SPD
* This product is in compliance with the RoHS directive.
Ordering Information
Part Number
Density Organization
Component Composition
HMT325R7AFR8A-G7/H9 2GB
HMT351R7AFR8A-G7/H9 4GB
HMT351R7AFR4A-G7/H9 4GB
HMT31GR7AFR8A-G7/H9 8GB
HMT31GR7AFR4A-G7/H9 8GB
HMT42GR7AMR4A-G7/H9 16GB
256Mx72
512Mx72
512Mx72
1Gx72
1Gx72
2Gx72
256Mx8(H5TC2G83AFR)*9
256Mx8(H5TC2G83AFR)*18
512Mx4(H5TC2G43AFR)*18
256Mx8(H5TC2G83AFR)*36
512Mx4(H5TC2G43AFR)*36
DDP 1Gx4(H5TC4G43AMR)*36
* In order to uninstall FDHS, please contact sales administrator
Rev. 0.1 / Nov. 2009
# of
ranks
FDHS
1X
2X
1X
4O
2O
4O
3
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Key Parameters
MT/s
Grade
DDR3-1066
DDR3-1333
-G7
-H9
Speed Grade
Grade
-G7
-H9
CL6
800
800
Address Table
tCK
(ns)
1.875
1.5
CAS
Latency
(tCK)
tRCD
(ns)
7 13.125
9 13.5
tRP
(ns)
13.125
13.5
tRAS
(ns)
37.5
36
tRC
(ns)
50.625
49.5
CL-tRCD-tRP
7-7-7
9-9-9
Frequency [MHz]
CL7
1066
1066
CL8
1066
1066
CL9
1333
CL10
1333
Remark
2GB(1Rx8) 4GB(2Rx8) 4GB(1Rx4) 8GB(4Rx8) 8GB(2Rx4) 16GB(4Rx4)
Refresh
Method
Row Address
Column
Address
Bank Address
Page Size
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
8K/64ms
A0-A13
A0-A9,A11
BA0-BA2
1KB
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
8K/64ms
A0-A13
A0-A9,A11
BA0-BA2
1KB
8K/64ms
A0-A13
A0-A9,A11
BA0-BA2
1KB
Rev. 0.1 / Nov. 2009
4
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Pin Descriptions
Pin Name
CK0
CK0
CK1
CK1
CKE[1:0]
RAS
CAS
WE
S[3:0]
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
SCL
SDA
SA[2:0]
Par_In
Err_Out
Description
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Num
ber
1
1
1
1
2
1
Column Address Strobe
1
Write Enable
1
Chip Selects
4
Address Inputs
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
Serial Presence Detect (SPD)
Clock Input
SPD Data Input/Output
SPD Address Inputs
Parity bit for the Address and
Control bus
Parity error found on the
Address and Control bus
14
1
1
3
1
1
3
1
1
Pin Name
Description
ODT[1:0]
DQ[63:0]
CB[7:0]
DQS[8:0]
DQS[8:0]
DM[8:0]/
DQS[17:9],
TDQS[17:9]
DQS[17:9],
TDQS[17:9]
EVENT
TEST
On Die Termination Inputs
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Masks / Data strobes,
Termination data strobes
Data strobes, negative line,
Termination data strobes
Reserved for optional hardware
temperature sensing
Memory bus test tool (Not Con-
nected and Not Usable on DIMMs)
RESET
Register and SDRAM control pin
VDD
VSS
VREFDQ
VREFCA
VTT
VDDSPD
Power Supply
Ground
Reference Voltage for DQ
Reference Voltage for CA
Termination Voltage
SPD Power
Num
ber
2
64
8
9
9
9
9
1
1
1
22
59
1
1
4
1
Rev. 0.1 / Nov. 2009
5
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