PRINCIPLES OF OPERATION
The X25170 is a 2K x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25170 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising SCK. CS must be LOW and the HOLD
and WP inputs must be HIGH during the entire opera-
tion. The WP input is “don’t care” if WPEN is set “0”.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are
transferred MSB ﬁrst.
Data input is sampled on the ﬁrst rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then resume operations. If the clock
line is shared with other peripheral devices on the SPI
bus, the user can assert the HOLD input to place the
X25170 into a “PAUSE” condition. After releasing
HOLD, the X25170 will resume operation from the
point when HOLD was ﬁrst asserted.
Write Enable Latch
The X25170 contains a “write enable” latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7 654 3 2 1 0
WPEN X X X BL1 BL0 WEL WIP
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
The Write-In-Process (WIP) bit indicates whether the
X25170 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25170 is divided into four 4096-bit seg-
ments. One, two, or all four of the segments may be
protected. That is, the user may read the segments but
will be unable to alter (write) data within the selected
segments. The partitioning is controlled as illustrated in
the following table.
Status Register Bits
Table 1. Instruction Set
Instruction Name Instruction Format*
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read status register
Write status register
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address (1 to 32 Bytes)
Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB ﬁrst.
Characteristics subject to change without notice. 3 of 15
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