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Preliminary Data Sheet
Specifications in this document are tentative and subject to change.
RX210 Group
Renesas MCUs
50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory,
12-bit AD, 10-bit DA, ELC, MPC, RTC, up to 9 comms interfaces;
incorporating functions for IEC60730 compliance
R01DS0041EJ0050
Rev.0.50
Apr 15, 2011
Features
32-bit RX CPU core
Max. operating frequency: 50 MHz
Capable of 78 DMIPS in operation at 50 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Low-power design and architecture
Operation from a single 1.62- to 5.5-V supply
1.62-V operation available (at up to 20 MHz)
Deep software standby mode with RTC remaining usable
Four low-power modes
On-chip flash memory for code, no wait states
50-MHz operation, 20-ns read cycle
No wait states for reading at full CPU speed
128- to 512-Kbyte capacities
User code programmable via the SCI
Programmable at 1.62 V
For instructions and operands
On-chip data flash memory
Eight Kbytes, reprogrammable up to TBD times
Erasing and programming impose no load on the CPU.
On-chip SRAM, no wait states
20- to 64-Kbyte size capacities
DMA
DMACA: Incorporates four channels
DTC: Four transfer modes
ELC
Module operation can be initiated by event signals
without going through interrupts.
Modules can operate while the CPU is sleeping.
Reset and supply management
Nine types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
Frequency of external clock: Up to 20 MHz
Frequency of the oscillator for sub-clock generation:
32.768 kHz
PLL circuit input: 4 to 12.5 MHz
On-chip low- and high-speed oscillators, dedicated on-
chip low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
Time capture on event-signal input through external pins
RTC capable of initiating return from deep software
standby mode
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch
PLQP0080JA-A 14 × 14 mm, 0.65-mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch
PLQP0064GA-A 14 × 14 mm, 0.8-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
Independent watchdog timer
125-kHz on-chip low-speed oscillator produces a
dedicated clock signal to drive IWDT operation.
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection functions for
the AD converter, clock-frequency accuracy-
measurement circuit, independent watchdog timer,
functions to assist in RAM testing, etc.
Up to nine communications interfaces
SCI with many useful functions (up to seven interfaces)
Asynchronous mode, clock synchronous mode, smart
card interface
I2C bus interface: Transfer at up to 1 Mbps, capable of
SMBus operation (1 interface)
RSPI (1)
External address spacewww.DataSheet.co.kr
Four CS areas (4 × 16 Mbytes)
8- or 16-bit bus space is selectable per area
Up to 14 extended-function timers
16-bit MTU2: input capture, output capture,
complementary PWM output, phase counting mode (6
channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
12-bit A/D converter
Capable of conversion within 1 μs
Sample-and-hold circuits (for three channels)
Three-channel synchronized sampling available
Self-diagnostic function and analog input disconnection
detection assistance function
10-bit D/A converter
Analog comparator
Programmable I/O ports
5-V tolerant, open drain, input pull-up, switching of
driving ability
MPC
Multiple locations are selectable for I/O pins of
peripheral functions
Temperature sensor
Operating temp. range
-40 C to +85C
R01DS0041EJ0050 Rev.0.50
Apr 15, 2011
Page 1 of 90
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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX210 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1 / 3)
Classification
CPU
Module/Function
CPU
Memory
ROM
RAM
E2 data flash
MCU operating mode
Clock
Clock generation circuit
Reset
Voltage detection Voltage detection circuit
(LVD)
Low power
consumption
Interrupt
Low power consumption
facilities
Interrupt control unit (ICU)
Description
Maximum operating frequency: 50 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 x 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
ROM capacity: 512 Kbytes (max.)
Three on-board programming modes
Boot mode (The user mat and the user boot mat are programmable via the SCI.)
User boot mode
User program mode
Parallel programmer mode (for off-board programming)
RAM capacity: 64 Kbytes (max.)
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E2 data flash capacity: 8 Kbytes
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode
(software switching)
Main clock oscillator, sub-clock oscillator, Low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, and dedicated low-speed on-chip oscillator for IWDT
Oscillation stop detection
Measuring circuit for accurcy of clock frequency (clock-accurcy check: CAC)
Independent frequency-division and multiplication settings for the system clock (ICLK), peripheral
module clock (PCLK), external bus clock (BCLK), and flashIF clock (FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 50 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at
max.)
Devices connected to the external bus run in synchronization with the external bus clock (BCLK):
12.5 MHz (at max.)
The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at
max.)
Pin reset, power-on reset, voltage-monitoring reset, watchdog timer reset, independent watchdog timer
reset, deep software standby reset, and software reset
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode
Interrupt vectors: 117
External interrupts: 9 (NMI and IRQ0 to IRQ7 pins)
Non-maskable interrupts: 6 (the NMI pin, oscillation stop detection interrupt, voltage-monitoring
interrupt 1, voltage-monitoring interrupt 2, WDT interrupt, and IWDT interrupt)
16 levels specifiable for the order of priority
R01DS0041EJ0050 Rev.0.50
Apr 15, 2011
Page 2 of 90
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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX210 Group
1. Overview
Table 1.1
Outline of Specifications (2 / 3)
Classification Module/Function
Description
External bus extension
The external address space can be divided into four areas (CS0 to CS3), each with independent
control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8- or 16-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
DMA
DMA controller (DMACA)
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
Data transfer controller
(DTC)
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
I/O ports
Programmable I/O ports
100-pin LQFP/80-pin LQFP/64-pin LQFP
I/O pin: 84/64/48
Input: 1/1/1
Pull-up resistors: 85/65/49
Open-drain outputs: 54/44/35
5-V tolerance: 4/4/2
Event link controller (ELC)
Event signals of 59 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for ports B and E
Multifunction pin controller (MPC)
Capable of selecting input/output function from multiple pins
Timers
Multi-function timer pulse
unit 2 (MTU2)
(16 bits x 6 channels) x 1 unit
Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, TCLKA, TCLKB, TCLKC, TCLKD) other than channel 5,
for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
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Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Port output enable2 (POE2) Controls the high-impedance state of the MTU2’s waveform output pins from multiple pins
8-bit timer (TMR)
(8 bits x 2 channels) x 2 units
Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32, PCLK/64,
PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Compare match timer
(CMT)
Watchdog timer (WDT)
(16 bits x 2 channels) x 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits x 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512,
PCLK/2048, PCLK/8192)
Independent watchdog
timer (IWDT)
14 bits x 1 channel
Counter-input clock: Dedicated low-speed on-chip oscillator for IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
Realtime clock (RTC)
Clock source: Subclock
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Time-capture facility for three values
R01DS0041EJ0050 Rev.0.50
Apr 15, 2011
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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX210 Group
1. Overview
Table 1.1
Outline of Specifications (3 / 3)
Classification
Communication
function
Module/Function
Serial communications
interfaces (SCIc, SCId)
I2C bus interface (RIIC)
Serial peripheral
interface (RSPI)
12-bit A/D converter
Temperature sensor
D/A converter
CRC calculator (CRC)
Comparator A
Comparator B
Power supply voltage/ Operating frequency
Supply current
Operating temperature
Package
Description
7 channels (channel 0, 1, 5, 6, 8, 9: SCIc, channel 12: SCId)
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers (SCL5, SCL6, and SCL12)
Simple IIC
Simple SPI
Master/slave mode supported (SCId only)
Start frame and information frame are included (SCId only)
1 channel
Communications formats:
I2C bus format/SMBus format
Master/slave selectable
Supports the first mode
1 channel
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32
bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
12 bits (16 channels x 1 unit)
12-bit resolution
Conversion time: 1.0 s per channel (in operation with ADCLK at 50 MHz)
Operating modes
Scan mode (single-cycle scan mode, continuous scan mode, and group scan mode)
Sample-and-hold function
Self-diagnosis for the A/D converter
Assistance in detecting disconnected analog inputs
Double-trigger mode (duplexing of A/D-converted data)
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A/D conversion start conditions
Conversion can be started by software, a conversion start trigger from a timer (MTU2), an external
trigger signal, or ELC.
Outputs the voltage that changes depending on the temperature
PGA gain switchable: Four levels according to the voltage range
2 channels
10-bit resolution
Output voltage: 0 V to VREFH
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
2 channels
Comparison of reference voltage and analog input voltage
2 channels
Comparison of reference voltage and analog input voltage
VCC = 1.62 to 5.5 V: 20 MHz (TBD),
VCC = 2.7 to 5.5 V: 50 MHz
TBD mA (typ.)
40 to +85C
100-pin TFLGA (PTLG0100JA-A)
100-pin LQFP (PLQP0100KB-A)
80-pin LQFP (PLQP0080KB-A)
80-pin LQFP (PLQP0080JA-A)
64-pin LQFP (PLQP0064KB-A)
64-pin LQFP (PLQP0064GA-A)
R01DS0041EJ0050 Rev.0.50
Apr 15, 2011
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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX210 Group
1. Overview
Table 1.2
Comparison of Functions for Different Packages
Module/Functions
External bus
CS areas: 4 (CS0 to CS3)
Interrupt
External interrupts
DMA
DMA controller (DMAC)
Data transfer controller (DTC)
Timers
Multi-function timer pulse unit 2 (MTU2)
Port output enable 2 (POE2)
8-bit timer (TMR)
Compare match timer (CMT)
Realtime clock (RTC)
Watchdog timer (WDT)
Independent watchdog timer (IWDT)
Communication Serial communications interface (SCIc)
function
Serial communications interface (SCId)
I2C bus interface (RIIC)
Serial peripheral interface (RSPI)
12-bit A/D converter
Temperature sensor
D/A converter
CRC calculator (CRC)
Event link controller (ELC)
Comparator A
Comparator B
Package
RX210 Group
100 Pins
80 Pins
64 Pins
Supported
Not supported
Not supported
NMI, IRQ0 to IRQ7
4 channels (DMAC0 to DMAC3)
Supported
6 channels (MTU0 to MTU5)
POE0# to POE3#, POE8#
2 channels × 2 units
2 channels × 2 units
Supported
Supported
Supported
6 channels
(SCI0, 1, 5, 6, 8, 9)
5 channels
(SCI1, 5, 6, 8, 9)
1 channel (SCI12)
1 channel
1 channel
16 channels
(AN000 to AN015)
14 channels
(AN000 to AN013)
12 channels
(AN000 to AN004,
AN006, AN008 to
AN013)
Supported
2 channels
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Supported
Supported
2 channels
2 channels
100-pin TFLGA
100-pin LQFP
80-pin LQFP
64-pin LQFP
R01DS0041EJ0050 Rev.0.50
Apr 15, 2011
Page 5 of 90
Datasheet pdf - http://www.DataSheet4U.net/