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Preliminary Datasheet
Specifications in this document are tentative and subject to change.
RX220 Group
Renesas MCUs
32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory,
12-bit A/D, ELC, MPC, RTC, up to 7 comms channels;
incorporating functions for IEC60730 compliance
R01DS0130EJ0051
Rev.0.51
May 24, 2012
Features
32-bit RX CPU core
Max. operating frequency: 32 MHz
Capable of 49 DMIPS in operation at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Low-power design and architecture
Operation from a single 1.62-V to 5.5-V supply
1.62-V operation available (at up to TBD MHz)
Three low-power modes
On-chip flash memory for code, no wait states
32-MHz operation, 31.25-ns read cycle
No wait states for reading at full CPU speed
Up to 256-Kbyte capacity
User code programmable via the SCI
Programmable at 1.62 V
For instructions and operands
On-chip data flash memory
8 Kbytes (Number of times of reprogramming: 100,000)
Erasing and programming impose no load on the CPU.
On-chip SRAM, no wait states
Up to 16-Kbyte size capacity
DMA
DMAC: Incorporates four channels
DTC: Four transfer modes
ELC
Module operation can be initiated by event signals
without going through interrupts.
Modules can operate while the CPU is sleeping.
Reset and supply management
Seven types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
Frequency of external clock: Up to 20 MHz
Frequency of the oscillator for sub-clock generation:
32.768 kHz
On-chip low- and high-speed oscillators, dedicated on-
chip low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5-mm pitch
Independent watchdog timer
125-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance
functions for the A/D converter, clock-frequency
accuracy-measurement circuit, independent watchdog
timer, functions to assist in RAM testing, etc.
Up to seven communications channels
SCI with many useful functions (up to five channels)
Asynchronous mode, clock synchronous mode, smart
card interface mode
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
RSPI (one channel)
Up to 14 extended-function timers
16-bit MTU: input capture, output capture,
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complementary PWM output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit compare-match timers (four channels)
12-bit A/D converter
Capable of conversion within 1.56 μs
Self-diagnostic function and analog input disconnection
detection assistance function
Analog comparator
General I/O ports
5-V tolerant, open drain, input pull-up, switching of
driving ability
MPC
Multiple locations are selectable for I/O pins of
peripheral functions
Operating temp. range
 40C to +85C
R01DS0130EJ0051 Rev.0.51
May 24, 2012
Page 1 of 48
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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX220 Group
1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different
packages.
Table 1.1 is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Outline of Specifications (1 / 3)
Classification
CPU
Module/Function
CPU
Memory
ROM
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Reset
Voltage detection Voltage detection circuit
(LVDAa)
Low power
consumption
Interrupt
Low power consumption
facilities
Function for lower
operating power
consumption
Interrupt controller (ICUb)
Description
Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
Capacity: 32 K/64 K/128 K/256 Kbytes
32 MHz, no-wait memory access
On-board programming: 3 types
Capacity: 4 K/8 K/16 Kbytes
32 MHz, no-wait memory access
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E2 DataFlash capacity: 8 Kbytes
Single-chip mode
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
and IWDT-dedicated on-chip oscillator
Oscillation stop detection
Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and flashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at
max.)
The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at
max.)
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels
Module stop function
Three low power consumption modes
Sleep mode, all-module clock stop mode, and software standby mode
Four operating power control modes
Middle-speed operating mode 1A, middle-speed operating mode 1B, low-speed operating mode 1,
low-speed operating mode 2
Interrupt vectors: 106
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 5 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)
16 levels specifiable for the order of priority
R01DS0130EJ0051 Rev.0.51
May 24, 2012
Page 2 of 48
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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX220 Group
1. Overview
Table 1.1
Outline of Specifications (2 / 3)
Classification
DMA
Module/Function
DMA controller (DMACA)
I/O ports
Data transfer controller
(DTCa)
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
(POE2a)
8-bit timer (TMR)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCb)
Description
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
100-pin LQFP/64-pin LQFP/48-pin LQFP
I/O pin: 84/48/34
Input: 1/1/1
Pull-up resistors: 84/48/34
Open-drain outputs: 35/26/20
5-V tolerance: 4/2/2
Event signals of 45 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for port B
Capable of selecting input/output function from multiple pins
(16 bits 6 channels) 1 unit
Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Controls the high-impedance state of the MTU’s waveform output pins
(8 bits 2 channels) 2 unitswww.DataSheet.co.kr
Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,
PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
(16 bits 2 channels) 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Frequency divided by 1, 16, 32, 64, 128, or 256
Clock source: Sub-clock
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
R01DS0130EJ0051 Rev.0.51
May 24, 2012
Page 3 of 48
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Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX220 Group
1. Overview
Table 1.1
Outline of Specifications (3 / 3)
Classification
Communication
function
Module/Function
Serial communications
interfaces (SCIc, SCId)
I2C bus interface (RIIC)
Serial peripheral
interface (RSPI)
12-bit A/D converter (S12ADb)
CRC calculator (CRC)
Comparator A (CMPA)
Data Operation Circuit (DOC)
Power supply voltage/Operating frequency
Supply current
Operating temperature
Package
Description
5 channels (channel 1, 5, 6, and 9: SCIc, channel 12: SCId)
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers (SCI5, SCI6, and SCI12)
Simple IIC
Simple SPI
Master/slave mode supported (SCId only)
Start frame and information frame are included (SCId only)
1 channel
Communications formats:
I2C bus format/SMBus format
Master/slave selectable
Supports the fast mode
1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPCK
(RSPI clock) signals enables serial transfer through SPI operation (four lines) or clock-synchronous
operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32
bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
12 bits (16 channels 1 unit)
12-bit resolution
Minimum conversion time: 1.56 s per channel (in operation with ADCLK at 32 MHz)
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Sample-and-hold function www.DataSheet.co.kr
Self-diagnosis for the A/D converter
Assistance in detecting disconnected analog inputs
Double-trigger mode (duplication of A/D conversion data)
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
CRC code generation for any desired data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
2 channels
Comparison of reference voltage and analog input voltage
Comparison, addition, and subtraction of 16-bit data
VCC = 1.62 to 1.8 V: 4 MHz (TBD), VCC = 1.8 to 2.7 V: 8 MHz (TBD), VCC = 2.7 to 5.5 V: 32 MHz
TBD mA (typ.)
40 to +85C
100-pin LQFP (PLQP0100KB-A)
64-pin LQFP (PLQP0064KB-A)
48-pin LQFP (PLQP0048KB-A)
R01DS0130EJ0051 Rev.0.51
May 24, 2012
Page 4 of 48
Datasheet pdf - http://www.DataSheet4U.net/

No Preview Available !

Under development Preliminary document
Specifications in this document are tentative and subject to change.
RX220 Group
1. Overview
Table 1.2
Comparison of Functions for Different Packages
Module/Functions
Interrupt
External interrupts
DMA
DMA controller
Data transfer controller
Timers
Multi-function timer pulse unit 2
Port output enable 2
8-bit timer
Compare match timer
Realtime clock
Independent watchdog timer
Communication Serial communications interface
function
(SCIc)
Serial communications interface
(SCId)
I2C bus interface
Serial peripheral interface
12-bit A/D converter
CRC calculator
Event link controller
Comparator A
Package
RX220 Group
100 Pins
64 Pins
48 Pins
NMI, IRQ0 to IRQ7
NMI, IRQ0 to IRQ2,
IRQ4 to IRQ7
NMI, IRQ0, IRQ1,
IRQ4 to IRQ7
4 channels (DMAC0 to DMAC3)
Supported
6 channels (MTU0 to MTU5)
POE0# to POE3#, POE8#
2 channels × 2 units
2 channels × 2 units
Supported
Not supported
Supported
4 channels
(SCI1, 5, 6, 9)
3 channels
(SCI1, 5, 6)
1 channel (SCI12)
16 channels
(AN000 to AN015)
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100-pin LQFP
1 channel
1 channel
12 channels
(AN000 to AN004,
AN006,
AN008 to AN013)
Supported
Supported
2 channels
64-pin LQFP
8 channels
(AN000, AN003,
AN004, AN006,
AN009 to AN012)
48-pin LQFP
R01DS0130EJ0051 Rev.0.51
May 24, 2012
Page 5 of 48
Datasheet pdf - http://www.DataSheet4U.net/