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Data Sheet
14-Bit, 170 MSPS/250 MSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9250
FEATURES
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 711 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self-test (BIST) capability
APPLICATIONS
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
I/Q demodulation systems
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
VIN+A
VIN–A
VCM
VIN+B
VIN–B
SYSREF±
SYNCINB±
CLK±
RFCLK
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD DVDD
AGND DGND DRGND
AD9250
PIPELINE
14-BIT ADC
PIPELINE
14-BIT ADC
JESD-204B
INTERFACE
HIGH
SPEED
SERIALIZERS
CONTROL
REGISTERS
CML, TX
OUTPUTS
SERDOUT0±
SERDOUT1±
CMOS
DIGITAL
INPUT/
OUTPUT
PDWN
CLOCK
GENERATION
CMOS
DIGITAL
INPUT/OUTPUT
FAST
DETECT
CMOS
DIGITAL
INPUT/
OUTPUT
FDA
FDB
RST
SDIO SCLK CS
Figure 1.
PRODUCT HIGHLIGHTS
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1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output block supports up to
5 Gbps per lane.
3. An on-chip, phase-locked loop (PLL) allows users to provide a
single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
4. Support for an optional RF clock input to ease system board
design.
5. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions such as controlling the clock
DCS, power-down, test modes, voltage reference mode, over
range fast detection, and serial output configuration.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9250
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
ADC DC Specifications ............................................................... 4
ADC AC Specifications ............................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 8
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 17
Theory of Operation ...................................................................... 18
ADC Architecture ...................................................................... 18
Analog Input Considerations.................................................... 18
Voltage Reference ....................................................................... 19
Clock Input Considerations ...................................................... 19
Power Dissipation and Standby Mode..................................... 22
REVISION HISTORY
10/12—Revision 0: Initial Version
Data Sheet
Digital Outputs ............................................................................... 23
ADC Overrange and Gain Control.......................................... 29
ADC Overrange (OR)................................................................ 29
Gain Switching............................................................................ 29
DC Correction ................................................................................ 31
DC Correction Bandwidth........................................................ 31
DC Correction Readback.......................................................... 31
DC Correction Freeze................................................................ 31
DC Correction (DCC) Enable Bits .......................................... 31
Built-In Self-Test (BIST) and Output Test .................................. 32
Built-In Self-Test......................................................................... 32
Serial Port Interface (SPI).............................................................. 33
Configuration Using the SPI..................................................... 33
Hardware Interface..................................................................... 33
SPI Accessible Features.............................................................. 34
Memory Map .................................................................................. 35
Reading the Memory Map Register Table............................... 35
Memory Map Register Table..................................................... 36
Memory Map Register Description ......................................... 40
Applicationswww.DataSheet.net/ Information .............................................................. 41
Design Guidelines ...................................................................... 41
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 42
Rev. 0 | Page 2 of 44
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Data Sheet
GENERAL DESCRIPTION
The AD9250 is a dual, 14-bit ADC with sampling speeds of up
to 250 MSPS. The AD9250 is designed to support communications
applications where low cost, small size, wide bandwidth, and
versatility are desired.
The ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC cores feature wide bandwidth inputs supporting a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance. The JESD204B
high speed serial interface reduces board routing requirements
and lowers pin count requirements for the receiving device.
AD9250
By default, the ADC output data is routed directly to the two
JESD204B serial output lanes. These outputs are at CML voltage
levels. Four modes support any combination of M = 1 or 2 (single
or dual converters) and L = 1 or 2 (one or two lanes). For dual
ADC mode, data can be sent through two lanes at the maximum
sampling rate of 250 MSPS. However, if data is sent through
one lane, a sampling rate of up to 125 MSPS is supported.
Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings,
when desired. Programmable overrange level detection is
supported for each channel via the dedicated fast detect pins.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface.
The AD9250 is available in a 48-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
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Rev. 0 | Page 3 of 44
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AD9250
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, duty cycle stabilizer (DCS) enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
DVDD
Supply Current
IAVDD
IDRVDD + IDVDD
POWER CONSUMPTION
Sine Wave Input
Standby Power4
Power-Down Power
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
14
−16
−6
−15
−2
1.7
1.7
1.7
AD9250-170
Typ Max
Guaranteed
+16
+2
±0.75
±0.25
±2.1
±1.5
+15
+3.5
±2
±16
1.49
1.75
2.5
20
0.9
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1.8 1.9
1.8 1.9
1.8 1.9
233 260
104 113
607
280
9
AD9250-250
Min Typ Max
14
Guaranteed
−16 +16
−6 +2.5
±0.75
±0.25
±3.5
±1.5
−15 +15
−2 +3
±2
±44
1.49
1.75
2.5
20
0.9
1.7 1.8 1.9
1.7 1.8 1.9
1.7 1.8 1.9
255 280
140 160
711
339
9
Unit
Bits
mV
%FSR
LSB
LSB
LSB
LSB
mV
%FSR
ppm/°C
ppm/°C
LSB rms
V p-p
pF
kΩ
V
V
V
V
mA
mA
mW
mW
mW
1 Measured with a low input frequency, full-scale sine wave.
2 Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Standby power is measured with a dc input and the CLK± pin active.
Rev. 0 | Page 4 of 44
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Data Sheet
AD9250
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
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25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
AD9250-170
AD9250-250
Min Typ Max Min Typ Max Unit
72.5
72.0
70.7
71.4
70.7
70.1
72.1
71.7
71.2
70.6
69.3
70.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
71.3
70.9
69.6
70.3
69.6
68.9
70.7
70.5
70.0
69.5
68.0
68.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
11.5 11.5 Bits
11.4 11.4 Bits
11.3 11.3 Bits
11.1 11.2 Bits
10.9 11.0 Bits
92
95
78
91
86
85
89
86
86
88
80
88
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−92
−95
−78
−91
−86
−85
−89 dBc
−87 dBc
dBc
−86 dBc
−88 dBc
−80 dBc
−88 dBc
−95
−94
−78
−97
−96
−93
−94 dBc
−96 dBc
dBc
−96 dBc
−88 dBc
−80 dBc
−91 dBc
Rev. 0 | Page 5 of 44
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