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PS21963-ET
MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-ET/-AET/-CET/-ETW
TRANSFER-MOLD TYPE
INSULATED TYPE
INTEGRATED POWER FUNCTIONS
600V/8A low-loss CSTBTTM inverter bridge for three
phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• For upper-leg IGBTS : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC), Over temperature protection (OT).
• Fault signaling : Corresponding to an SC fault (Lower-leg IGBT), a UV fault (Lower-side supply) or an OT fault (LVIC temperature).
• Input interface : 3V, 5V line (High Active).
• UL Approved : Yellow Card No. E80276
APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES (PS21963-ET)
0.28
1.778 ±0.2
38 ±0.5
20×1.778(=35.56)
35 ±0.3
A
16-0.5
17 1
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B
2-R1.6
QR Type name
Code Lot No.
3 MIN
18
0.28
2.54 ±0.2
0.5
14×2.54 (=35.56)
25
8-0.6
4-C1.2
0.5 0.5
0.5
2.5 MIN
(2.656)
3.5
1.5 ±0.05
0.8
HEAT SINK SIDE
Dimensions in mm
TERMINAL CODE
1. NC
2. VUFB
3. VVFB
4. VWFB
5. UP
6. VP
7. WP
8. VP1
9. VNC *
10. UN
11. VN
12. WN
13. VN1
14. FO
15. CIN
16. VNC *
17. NC
18. NC
19. NC
20. N
21. W
22. V
23. U
24. P
25. NC
1.5 MIN
HEAT SINK SIDE
(2.756)
(1.2)
DETAIL A
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
Aug. 2007
Datasheet pdf - http://www.DataSheet4U.co.kr/

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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-ET/-AET/-CET/-ETW
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 LONG TERMINAL TYPE PACKAGE OUTLINES (PS21963-AET)
38 ±0.5
A
B
20×1.778(=35.56)
0.28
35 ±0.3
1.778 ±0.2
16-0.5
17 1
3.5
1.5 ±0.05
2-R1.6
QR Type name
Code Lot No.
3 MIN
18
0.28
2.54 ±0.2
0.5
14×2.54 (=35.56)
25
8-0.6
4-C1.2
0.5 0.5
0.5
2.5 MIN
(2.656)
0.8
HEAT SINK SIDE
Dimensions in mm
TERMINAL CODE
1. NC
2. VUFB
3. VVFB
4. VWFB
5. UP
6. VP
7. WP
8. VP1
9. VNC *
10. UN
11. VN
12. WN
13. VN1
14. FO
15. CIN
16. VNC *
17. NC
18. NC
19. NC
20. N
21. W
22. V
23. U
24. P
25. NC
1.5 MIN
(1.2)
(2.756)
HEAT SINK SIDE
DETAIL A
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
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Fig. 3 ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21963-CET)
38 ±0.5
A
B
20×1.778(=35.56)
0.28
1.778 ±0.2
35 ±0.3
16-0.5
3.5
1.5 ±0.05
17 1
2-R1.6
QR Type name
Code Lot No.
3 MIN
18
0.28
2.54 ±0.2
0.5
25
8-0.6
4-C1.2
14×2.54 (=35.56)
0.5
0.5
(2.656)
0.8
HEAT SINK SIDE
Dimensions in mm
TERMINAL CODE
1. NC
2. VUFB
3. VVFB
4. VWFB
5. UP
6. VP
7. WP
8. VP1
9. VNC *
10. UN
11. VN
12. WN
13. VN1
14. FO
15. CIN
16. VNC *
17. NC
18. NC
19. NC
20. N
21. W
22. V
23. U
24. P
25. NC
1.5 MIN
(1.2)
(2.756)
HEAT SINK SIDE
DETAIL A
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
Aug. 2007
2
Datasheet pdf - http://www.DataSheet4U.co.kr/

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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-ET/-AET/-CET/-ETW
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 4 BOTH SIDES ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21963-ETW)
0.28
1.778 ±0.25
38 ±0.5
20×1.778(=35.56)
35 ±0.3
A
16-0.5
B
3.5
1.5 ±0.05
17 1
2-R1.6
QR Type name
Code Lot No.
3 MIN
18
0.28
2.54 ±0.25
14×2.54 (=35.56)
0.5 0.5
25
7-0.6
4-C1.2
2.5 MIN
0.5
(2.656)
0.8
HEAT SINK SIDE
Dimensions in mm
TERMINAL CODE
1. NC
2. VUFB
3. VVFB
4. VWFB
5. UP
6. VP
7. WP
8. VP1
9. VNC *
10. UN
11. VN
12. WN
13. VN1
14. FO
15. CIN
16. VNC *
17. NC
18. NC
19. NC
20. N
21. W
22. V
23. U
24. P
25. NC
1.5 MIN
(1.2)
(2.756)
HEAT SINK SIDE
DETAIL A
DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
Fig. 5 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
C1 : Electrolytic type with good temperature and frequency
characteristics
(Note : The capacitance value depends on the PWM control
scheme used in the applied system).
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
Inrush current
limiter circuit
P
AC line input
(Note 4)
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High-side input (PWM)
(3V, 5V line)(Note 1, 2)
Input signal Input signal Input signal
conditioning conditioning conditioning
Level shifter
Protection
circuit (UV)
Level shifter
Level shifter
Drive circuit Drive circuit Drive circuit
C2
C1
(Note 6)
(Note 5)
H-side IGBTS
DIP-IPM
U
V
W
(Note 7)
M
AC line output
ZC
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line
surge absorber circuit may become necessary
depending on the application environment).
N1
VNC
CIN
N
Drive circuit
L-side IGBTS
Input signal conditioning Fo logic
Protection
circuit
Control supply
Under-Voltage
protection
Note1:
2:
3:
4:
5:
6:
7:
Low-side input (PWM) FO
(3V, 5V line)(Note 1, 2) Fault output (5V line)
(Note 3)
(Note 6)
VNC
VD
(15V line)
Input logic is high-active. There is a 3.3k(min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 11)
This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kresistor.
(see also Fig. 11)
The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P & N1 DC power input pins.
High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.
Aug. 2007
3
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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-ET/-AET/-CET/-ETW
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 6 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
P
Drive circuit
External protection circuit
H-side IGBTS
L-side IGBTS
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection
U Trip Level
V
W
N1
Shunt Resistor
AN
(Note 1)
CR
VNC
Drive circuit
CIN
B
Protection circuit
C
(Note 2)
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs.
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
0
Collector current
waveform
2 tw (µs)
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
Condition
Ratings
Unit
VCC
VCC(surge)
VCES
±IC
±ICP
PC
Tj
Supply voltage
Supply voltage (surge)
Collector-emitter voltage
Each IGBT collector current
Each IGBT collector current (peak)
Collector dissipation
Junction temperature
Applied between P-N
Applied between P-N
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TC = 25°C
TC = 25°C, less than 1ms
TC = 25°C, per 1 chip
(Note 1)
450
500
600
8
16
24.3
–20~+125
V
V
V
A
A
W
°C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC 100°C). However, to
ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125°C (@ TC 100°C).
CONTROL (PROTECTION) PART
Symbol
VD
VDB
Parameter
Control supply voltage
Control supply voltage
VIN Input voltage
VFO Fault output supply voltage
IFO Fault output current
VSC Current sensing input voltage
Condition
Applied between VP1-VNC, VN1-VNC
Applied between VUFB-U, VVFB-V, VWFB-W
Applied between UP, VP, WP, UN, VN,
WN-VNC
Applied between FO-VNC
Sink current at FO terminal
Applied between CIN-VNC
Ratings
20
20
–0.5~VD+0.5
–0.5~VD+0.5
1
–0.5~VD+0.5
Unit
V
V
V
V
mA
V
Aug. 2007
4
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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-ET/-AET/-CET/-ETW
TRANSFER-MOLD TYPE
INSULATED TYPE
TOTAL SYSTEM
Symbol
Parameter
VCC(PROT)
Self protection supply voltage limit
(short circuit protection capability)
TC Module case operation temperature
Tstg Storage temperature
Viso Isolation voltage
Condition
VD = 13.5~16.5V, Inverter part
Tj = 125°C, non-repetitive, less than 2µs
(Note 2)
60Hz, Sinusoidal, 1 minute,
Between pins and heat-sink plate
Ratings
400
–20~+100
–40~+125
1500
Unit
V
°C
°C
Vrms
Note 2: TC measurement point
Control terminals
DIP-IPM
11.6mm
3mm
IGBT chip position
FWD chip position
Power terminals
TC point
Heat sink side
THERMAL RESISTANCE
Symbol
Rth(j-c)Q
Rth(j-c)F
Parameter
Junction to case thermal
resistance
(Note 3)
Condition
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Inverter IGBT part (per 1/6 module)
Inverter FWD part (per 1/6 module)
Limits
Unit
Min. Typ. Max.
— — 4.1 °C/W
— — 5.4 °C/W
Note 3 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.
The contacting thermal resistance between DIP-IPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal
conductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and
the thermal conductivity is 1.0W/m·k.
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Parameter
VCE(sat)
VEC
ton
trr
tc(on)
toff
tc(off)
ICES
Collector-emitter saturation
voltage
FWD forward voltage
Switching times
Collector-emitter cut-off
current
Condition
VD = VDB = 15V
IC = 8A, Tj = 25°C
VIN = 5V
IC = 8A, Tj = 125°C
Tj = 25°C, –IC = 8A, VIN = 0V
VCC = 300V, VD = VDB = 15V
IC = 8A, Tj = 125°C, VIN = 0 5V
Inductive load (upper-lower arm)
VCE = VCES
Tj = 25°C
Tj = 125°C
Limits
Unit
Min. Typ. Max.
1.70 2.20
1.80 2.30 V
— 1.90 2.35 V
0.60 1.10 1.70 µs
— 0.30 — µs
0.40
0.60
µs
1.40
2.00
µs
0.40
0.75
µs
——
1
mA
10
Aug. 2007
5
Datasheet pdf - http://www.DataSheet4U.co.kr/