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HT82M99E/HT82M99A
USB Mouse Encoder 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Flexible total solution for applications that combine
PS/2 and low-speed USB interface, such as mice,
joysticks, and many others
· USB Specification Compliance
- Conforms to USB specification V2.0
- Conforms to USB HID specification V2.0
· Supports 1 Low-speed USB control endpoint and
1 interrupt endpoint
· Each endpoint has 8 bytes FIFO
· Integrated USB transceiver
· 3.3V regulator output
· External 6MHz or 12MHz ceramic resonator or
crystal
· 8-bit RISC microcontroller, with 2K´14 EPROM
(000H~7FFH)
· 96 bytes RAM (20H~7FH)
· 6MHz/12MHz internal CPU clock
· 4-level stacks
· Two 7-bit indirect addressing registers
· One 16-bit programmable timer counter with
overflow interrupt (shared with PA7, vector 0CH)
· One USB interrupt input (vector 04H)
· HALT function and wake-up feature reduce
power consumption
· PA0~PA7, PB4 and PB7 support wake-up function
· Internal Power-On reset (POR)
· Watchdog Timer (WDT)
· 12 I/O ports
· 16-pin NSOP, 18-pin DIP/SOP and
20-pin DIP/SOP/SSOP (150mil) package
General Description
The USB MCU OTP body is suitable for USB mouse de-
vices. It consists of a Holtek high performance 8-bit
MCU core for control unit, built-in USB SIE, 2K´14 ROM
and 96 bytes data RAM.
The mask version HT82M99A is fully pin and functionally
compatiblewww.DataSheet.net/ with the OTP version HT82M99E device.
Rev. 2.60
1 April 1, 2011
Datasheet pdf - http://www.DataSheet4U.co.kr/

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HT82M99E/HT82M99A
Block Diagram
U S B D + /C L K U S B D -/D A T A V 3 3 O
P ro g ra m
ROM
P ro g ra m
C o u n te r
U S B 1 .1
PS2
BP
STAC K
In te rru p t
C ir c u it
IN T C
In s tr u c tio n
R e g is te r
MP M
U
X
D ATA
M e m o ry
In s tr u c tio n
D ecoder
T im in g
G e n e ra to r
M UX
A LU
S h ifte r
STATU S
T M R L M fS Y S /4
TM R H
U
X P A 7 /T M R
TM R C
W D TS
W D T P r e s c a le r
E N /D IS
W DT
M
U
X
S Y S C L K /4
W DT O SC
PAC PO RT A
PA
P A 0~P A 6
P A 7 /T M R
PBC PO RT B
PB
P B 2~P B 4,
PB7
O SC2
O SC1
RES
VDD
VSS
Pin Assignment
ACC
www.DataSheet.net/
VSS
V 33O
U S B D + /C L K
U S B D -/D A T A
RES
PA0
PA1
PA2
1
2
3
4
5
6
7
8
16 O S C 1
15 O S C 2
14 V D D
1 3 P A 7 /T M R
12 P A 6
11 P A 5
10 P A 4
9 PA3
H T 8 2 M 9 9 E /H T 8 2 M 9 9 A
1 6 N S O P -A
VSS
V 33O
U S B D + /C L K
U S B D -/D A T A
RES
PA0
PA1
PB2
PB3
1
2
3
4
5
6
7
8
9
18 O S C 1
17 O S C 2
16 V D D
1 5 P A 7 /T M R
14 P A 6
13 P A 5
12 P A 4
11 P A 3
10 P A 2
H T 8 2 M 9 9 E /H T 8 2 M 9 9 A
1 8 D IP -A /S O P -A
VSS
V 33O
U S B D + /C L K
U S B D -/D A T A
RES
PA0
PA1
PB2
PB3
PB4
1
2
3
4
5
6
7
8
9
10
20 O S C 1
19 O S C 2
18 V D D
1 7 P A 7 /T M R
16 P A 6
15 P A 5
14 P A 4
13 P A 3
12 P A 2
11 P B 7
H T 8 2 M 9 9 E /H T 8 2 M 9 9 A
2 0 D IP -A /S O P -A /S S O P -A
Rev. 2.60
2 April 1, 2011
Datasheet pdf - http://www.DataSheet4U.co.kr/

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HT82M99E/HT82M99A
Pin Description
Pin Name I/O
ROM Code
Option
Description
PA0~PA6,
PA7/TMR
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by ROM code option. The input or output mode is con-
I/O
Pull-low
Pull-high
Wake-up
CMOS/NMOS/PMOS
trolled by PAC (PA control register).
Pull-high resistor options: PA0~PA7
Pull-low resistor options: PA0~PA3
CMOS/NMOS/PMOS options: PA0~PA7
Falling edge wake-up options: PA0~PA1, PA4~PA7
Rising and falling edge wake-up options: PA2~PA3
PA7 is wire-bonded with TMR
PB2, PB3
I/O
Pull-high
Pull-low
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined
by pull-high options).
Pull-low resistor for options: PB2, PB3
PB4, PB7
I/O
Pull-high
Wake-up
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined
by pull-high options).
Falling edge wake-up options: PB4, PB7
VSS ¾ ¾ Negative power supply, ground
RES I ¾ Schmitt trigger reset input. Active low.
VDD ¾ ¾ Positive power supply
V33O
O
¾ 3.3V regulator output
USBD+/CLK I/O
¾
USBD+ or PS2 CLK I/O line
USB or PS2 function is controlled by software control register
USBD-/DATA I/O
¾
USBD- or PS2 DATA I/O line
USB or PS2 function is controlled by software control register
OSC1
OSC2
I
O
OSC1, OSC2 are connected to a 6MHz or 12MHz crystal/resonator
¾
www.DataSheet.net/
(determined by software instructions) for the internal system clock.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...............................0°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 2.60
3 April 1, 2011
Datasheet pdf - http://www.DataSheet4U.co.kr/

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HT82M99E/HT82M99A
D.C. Characteristics
Ta=25°C
Symbol
Parameter
VDD
IDD
ISTB1
ISTB2
ISTB3
VIL1
VIH1
VIL2
VIH2
IOL
IOH
IOL2
IOH2
RPD
RPH1
RPH2
RPH3
VLVR
Operating Voltage
Operating Current (6MHz Crystal)
Standby Current
Standby Current (WDT Enabled)
Standby Current (WDT Disabled)
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
Input High Voltage (RES)
Output Sink Current for PA4~PA7,
PB4, PB7
Output Source Current for PA4~PA7,
PB4, PB7
Output Sink Current for PA0~PA3,
PB2~PB3
Output Source Current for PA0~PA3,
PB2~PB3
Pull-down Resistance for PA0~PA3,
PB2~PB3
Pull-high Resistance for DATA*
Pull-high Resistance for CLK
Pull-high Resistance for PA0~PA7,
PB2~PB4, PB7
Low Voltage Reset
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
¾ ¾ 3.3 ¾ 5.5 V
5V No load, fSYS=6MHz
¾7
9 mA
5V
No load, system HALT,
USB suspend**
¾
¾ 500 mA
5V No load, system HALT, ¾ ¾ 30 mA
input/output mode,
5V set SUSPEND2 [1CH].4 ¾ ¾ 20 mA
5V ¾
0 ¾ 0.8 V
5V ¾
2
¾ VDD
V
5V ¾
0 ¾ 0.4VDD V
5V ¾ 0.9VDD ¾ VDD V
5V VOL=0.4V
2 4 ¾ mA
5V VOH=3.4V
-2.5 -4 ¾ mA
5V VOL=0.4V
10 15 ¾ mA
5V VOH=3.4V
8 12 ¾ mA
5V
¾
¾
www.DataSheet.net/
¾
5V
¾
¾
¾
¾
¾
10 30 50 kW
1.3 1.5 2.0 kW
2.0 4.7 6.0 kW
30 50 70 kW
2.4 2.7 3
V
Note: ²*² The DATA pull-high must be implemented by the external 1.5kW.
²**² include 15kW loading of USBD+, USBD- line in host terminal.
A.C. Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD Conditions
Min.
fSYS System Clock (Crystal OSC)
5V ¾
6
fRCSYS RC Clock with 8-bit Prescaler Register
5V
¾
0
tWDT
Watchdog Time-out Period (System Clock) ¾ Without WDT prescaler 1024
tRF USBD+, USBD- Rising & falling Time
¾
¾
75
tRES External Reset Low Pulse Width ¾ ¾
1
tSST System Start-up Timer Period
¾ Wake-up from HALT
¾
tOSC
Crystal Setup
¾¾
¾
Typ.
¾
32
¾
¾
¾
1024
5
Max. Unit
12 MHz
¾ kHz
¾ tRCSYS
300 ns
¾ ms
¾ tSYS
10 ms
Note: Power-on period=tWDT+tSST+tOSC
WDT Time-out in normal mode=1/fRCSYS´256´WDTS+tWDT
WDT Time-out in HALT mode=1/fRCSYS´256´WDTS+tSST+tOSC
Rev. 2.60
4 April 1, 2011
Datasheet pdf - http://www.DataSheet4U.co.kr/

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HT82M99E/HT82M99A
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either 6MHz or 12MHz crystal oscillator, which used a
frequency that is determined by the SCLKSEL bit of the
SCC Register. The default system frequency is 12MHz.
The system clock is internally divided into four non-
overlapping clocks. One instruction cycle consists of
four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading to the PCL register, performing a sub-
routine call or return from subroutine, initial reset,
internal interrupt, external interrupt or return from inter-
rupts, the PC manipulates the program transfer by load-
ing the address corresponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
When a control transfer takes place, an additional
dummy cycle is required.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC PC
PC +1 PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
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F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Program Counter
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset
00000000000
USB Interrupt
00000000100
Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 1 0 0
Skip
Program Counter+2
Loading PCL
*10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
#10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Note: *10~*0: Program counter bits
#10~#0: Instruction code bits
Program Counter
S10~S0: Stack register bits
@7~@0: PCL bits
Rev. 2.60
5 April 1, 2011
Datasheet pdf - http://www.DataSheet4U.co.kr/