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LPC3152/3154
ARM926EJ microcontrollers with USB High-speed OTG,
SD/MMC, NAND flash controller, and audio codec
Rev. 1 — 31 May 2012
Product data sheet
1. General description
The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB
2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, an
integrated audio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and
parallel interfaces in a single chip targeted at consumer, industrial, medical, and
communication markets. To optimize system power consumption, the LPC3152/3154
have multiple power domains and a very flexible Clock Generation Unit (CGU) that
provides dynamic clock gating and scaling.
The LPC3152/3154 are implemented as a multi-chip module with two side-by-side dies,
one for digital functions and one for analog functions, which include Power Supply Unit
(PSU), audio codec, RTC, and Li-ion battery charger.
2. Features and benefits
2.1 Key features
CPU platform
www.DataSheet.net/
180 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)
Internal memory
192 kB embedded SRAM
External memory interface
NAND flash controller with 8-bit ECC and AES decryption engine (LPC3154 only)
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM
Security
AES decryption engine (LPC3154 only)
Secure one-time programmable memory for AES key storage and customer use
128 bit unique ID per device for DRM schemes
Communication and connectivity
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I2S-bus interfaces
Integrated master/slave SPI
Two master/slave I2C-bus interfaces
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
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NXP Semiconductors
LPC3152/3154
ARM926EJ microcontrollers
Three-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface
Integrated audio codec with stereo ADC and Class AB headphone amplifier
System functions
Dynamic clock gating and scaling
Multiple power domains
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB
On the LPC3154 only: secure booting using AES decryption engine from SPI flash,
NAND flash, SD/MMC cards, UART, or USB
DMA controller
Four 32-bit timers
Watchdog timer
PWM module
Master/slave PCM interface
Random Number Generator (RNG)
General Purpose I/O (GPIO) pins
Flexible and versatile interrupt structure
JTAG interface with boundary scan and ARM debug access
Real-Time Clock (RTC)
Power supply
Integrated power supply unit
Li-ion charger
USB charge pump
www.DataSheet.net/
Operating voltage and temperature
Core voltage: 1.2 V
I/O voltage: 1.8 V, 3.3 V
Temperature: 40 C to +85 C
TFBGA208 package: 12 12 mm2, 0.7 mm pitch
3. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC3152FET208 TFBGA208 TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls;
body 12 x 12 x 0.7 mm
LPC3154FET208 TFBGA208 TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls;
body 12 x 12 x 0.7 mm
Version
SOT930-1
SOT930-1
LPC3152_54
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 May 2012
© NXP B.V. 2012. All rights reserved.
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NXP Semiconductors
LPC3152/3154
ARM926EJ microcontrollers
3.1 Ordering options
Table 2. Ordering options for LPC3152/54
Type number
Total NAND
Security High-speed
SRAM Flash
engine USB
Controller AES
LPC3152FET208 192 kB yes
LPC3154FET208 192 kB yes
no Device/
Host/OTG
yes Device/
Host/OTG
10-bit Audio
ADC
codec,
channels PSU,
RTC,
Li-ion
charger
3 yes
3 yes
MCI
SDHC/
SDIO/
CE-ATA
yes
yes
Pins
208
208
Temperature
range
40 C to
+85 C
40 C to
+85 C
www.DataSheet.net/
LPC3152_54
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 May 2012
© NXP B.V. 2012. All rights reserved.
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4. Block diagram
LPC3152/3154
ARM926EJ microcontrollers
JTAG
TEST/DEBUG
INTERFACE
ARM926EJ-S
LPC3152/3154
DMA
USB 2.0
HIGH-SPEED
OTG
INTERRUPT
CONTROLLER
slave
slave
MPMC
slave
master master
master
master
MULTI-LAYER AHB MATRIX
slave
slave
ROM
slave
slave
96 kB ISRAM0
96 kB ISRAM1
MCI
SD/SDIO
slave
slave
slave
slave
slave
slave
NAND
CONTROLLER
AES(1) BUFFER
slave
WDT
AHB TO
APB
BRIDGE 0
AHB TO
APB
BRIDGE 1
AHB TO
APB
BRIDGE 4
AHB TO
APB
BRIDGE 3
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AHB TO
APB
BRIDGE 2
UART
SYSTEM
CONTROL
CGU
IOCONFIG
10-bit ADC
LCD
SPI
PCM
I2S0
EVENT
ROUTER
RNG
OTP
TIMER 0/1/2/3
PWM
I2C0
I2S1
NAND
REGISTERS
DMA
REGISTERS
I2C1
AUDIO
CODEC
Li-ION
CHARGER
ANALOG
DIE
USB
CHARGE
PUMP
PSU
RTC
(1) AES decryption engine available in LPC3154 only.
Fig 1. LPC3152/3154 block diagram
LPC3152_54
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 May 2012
002aae095
© NXP B.V. 2012. All rights reserved.
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LPC3152/3154
ARM926EJ microcontrollers
5. Pinning information
5.1 Pinning
ball A1
index area 2 4 6 8 10 12 14 16
1 3 5 7 9 11 13 15 17
A
B
C
D
E
F
G
H
J LPC3152/
K LPC3154
L
M
N
P
R
T
U
002aae464
Transparent top view
Fig 2. LPC3152/3154 pinning TFBGA208 package
Table 3. Pin allocation table
www.DataSheet.net/
Pin names with prefix m are multiplexed pins. See Table 11 for pin function selection of multiplexed pins.
Pin Symbol
Pin Symbol
Pin Symbol
Pin Symbol
Row A
1 n.c.
2 EBI_A_1_CLE
3 EBI_D_9
4 VDDE_IOC
5 VSSE_IOC
6 VDDI
7 VSSI
8 SPI_MISO
9 I2C_SCL0
10 FFAST_IN
11 n.c.
12 n.c.
13 ADC10B_GNDA
14 VSSE_IOC
15 VDDE_IOC
16 HP_VDDA33
17 n.c.
-
-
-
Row B
1 n.c.
2 n.c.
3 n.c.
4 n.c.
5 mNAND_RYBN0
6 mGPIO9
7 mGPIO6
8 SPI_MOSI
9 n.c.
10 FFAST_OUT
11 VDDA12
12 ADC10B_GPA0
13 ADC10B_VDDA33
14 n.c.
15 HP_FCR
16 HP_GNDA
17 HP_OUTL
-
-
-
Row C
1 n.c.
2 EBI_D_10
3 n.c.
4 EBI_A_0_ALE
5 mNAND_RYBN1
6 mGPIO10
7 mGPIO7
8 SPI_SCK
9 VPP
10 I2C_SDA0
11 VSSA12
12 ADC10B_GPA2
13 ADC10B_GPA1
14 DAC_VDDA33
15 HP_OUTR
16 HP_FCL
17 PSU_PLAY
-
-
-
Row D
1 VDDE_IOA
2 EBI_D_11
3 EBI_D_8
4 mNAND_RYBN3
LPC3152_54
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 31 May 2012
© NXP B.V. 2012. All rights reserved.
5 of 94
Datasheet pdf - http://www.DataSheet4U.co.kr/