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Rad Hard and SEE Hard 6A Synchronous Buck Regulator
ISL70001ASEH
The ISL70001ASEH is a radiation hardened and SEE hardened
high efficiency monolithic synchronous buck regulator with
integrated MOSFETs. This single chip power solution operates
over an input voltage range of 3V to 5.5V and provides a tightly
regulated output voltage that is externally adjustable from 0.8V
to ~85% of the input voltage. Output load current capacity is 6A
for TJ < +145°C.
The ISL70001ASEH utilizes peak current-mode control for
excellent output load transient response and features integrated
compensation and switches at a fixed frequency of 1MHz to
reduce component size and count. In application where two POLs
are needed, two ISL70001ASEH devices can be synchronized
180° out-of-phase to reduce the overall input RMS ripple current.
The internal synchronous power switches are optimized for high
efficiency and good thermal performance.
The ISL70001ASEH incorporates fault protection for the
regulator. The protection circuits include input undervoltage,
output undervoltage, and output overcurrent.
High integration and class leading radiation tolerance makes
the ISL70001ASEH an ideal choice to power many of today’s
small form factor applications. Two devices can be
synchronized to provide a complete power solution for large
scale digital ICs, like field programmable gate arrays (FPGAs),
that require separate core and I/O voltages.
Applications
• FPGA, CPLD, DSP, CPU Core or I/O Voltages
• Low-Voltage, High-Density Distributed Power Systems
Related Literature
• ISL70001ASEHEV1Z Evaluation Board, AN1842
Features
• ±1% Reference Voltage Over Line, Load, Temperature and
Radiation
• Current Mode Control for Excellent Dynamic Response
• Full Mil-Temp Range Operation (TA = -55°C to +125°C)
• 50% Lower Shutdown Supply Current than the ISL70001SEH
• Available in a thermally enhanced heatsink package - R48.B
• Highly Efficient: 94% Peak Efficiency
• Operates from 3V to 5.5V Supply
• Adjustable Output Voltage
- Two External Resistors Set VOUT from 0.8V to ~85% of VIN
• Bi-directional SYNC Pin Allows Two Devices to be Synchronized
180° Out-of-Phase
• Power-Good Output Voltage Monitor
• Adjustable Analog Soft-Start
• Input Undervoltage, Output Undervoltage and Output
Overcurrent Protection
• Electrically Screened to DLA SMD 5962-09225
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardness
- Total Dose [50-300rad(Si)/s] . . . . . . . . . . . . . . 100krad(Si)
http://www.DataSheet4U.net/
- Total Dose [<10mrad(Si)/s] . . . . . . . . . . . . . . 100krad(Si)*
* Product capability established by initial characterization. The
EH version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
• SEE Hardness
- SEL and SEB LETeff . . . . . . . . . . . . 86.4MeV/mg/cm2 min
- SEFI X-section (LETeff = 86.4MeV/mg/cm2) 1.4 x 10-6 cm2
max
- SET LETeff (< 1 Pulse Perturbation) 86.4MeV/mg/cm2 min
5V Supply
ISL70001ASEH
SYNCH
ISL75051SEH
ISL70001ASEH
SYNCH
CORE
AUX
RAD TOLERANT
FPGA
I/O
FIGURE 1. TYPICAL APPLICATION
100
95
90
85
1.5V
1.8V
80
2.5V
3.3V
1.2V
75
70
012345
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY 5V INPUT, TA = +25°C
6
May 22, 2013
FN8365.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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ISL70001ASEH
Functional Block Diagram
PORSEL
SS
FB
PGOOD
REF
SYNC
M/S
POWER-ON
RESET (POR)
SOFT
START
SLOPE
COMPENSATION
EA GM
COMPENSATION
PWM
CONTROL
LOGIC
CURRENT
SENSE
GATE
DRIVE
UV
POWER-GOOD
PWM
REFERENCE
0.6V
http://www.DataSheet4U.net/
PGNDx
BIT
TRIM
AVDD
DVDD
PVINx
LXx
PGNDx
TDI
TDO
ZAP
PGNDx
Ordering Information
ORDERING NUMBER
(Note 1)
PART NUMBER
TEMP. RANGE
(°C)
PACKAGE (Note 3)
(RoHS Compliant)
PKG.
DWG. #
5962R0922503VXC
ISL70001ASEHVF (Note 2)
-55 to +125
48 Ld CQFP
R48.A
5962R0922503VYC
ISL70001ASEHVFE (Note 2)
-55 to +125
48 Ld CQFP with Heatsink R48.B
5962R0922503V9A
ISL70001ASEHVX
-55 to +125
Die
ISL70001ASEHF/PROTO
ISL70001ASEHF/PROTO (Note 2)
-55 to +125
48 Ld CQFP
R48.A
ISL70001ASEHFE/PROTO ISL70001ASEHFE/PROTO (Note 2)
-55 to +125
48 Ld CQFP with Heatsink R48.B
ISL70001ASEHX/SAMPLE ISL70001SEHX/SAMPLE
-55 to +125
Die
ISL70001ASEHEV1Z
ISL70001ASEHEV1Z
Evaluation Board
NOTES:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed in the Ordering Information table on page 2 must be used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant
and compatible with both SnPb and Pb-free soldering operations.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL70001ASEH. For more information on MSL,
please see Tech Brief TB363.
2 FN8365.0
May 22, 2013
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Pin Configuration
ISL70001ASEH
ISL70001ASEH
(48 LD CQFP)
TOP VIEW
M/S
ZAP
TDI
TDO
PGOOD
SS
DVDD
DVDD
DGND
DGND
AGND
AGND
6 5 4 3 2 1 48 47 46 45 44 43
7 42
8 41
9 40
10 39
11 38
12 37
13 * HEATSINK 36
14 35
15 34
16 33
17 32
1819
20
21
22
23
24
25
26
27
28
29
31
30
PVIN3
LX3
PGND3
PGND3
PGND4
PGND4
LX4
PVIN4
PVIN4
PVIN5
PVIN5
LX5
Pin Descriptions
PIN NUMBER
1, 2, 27, 28, 29, 30,
37, 38, 39, 40, 47,
48
3, 26, 31, 36, 41,
46
PIN NAME
PGNDx
LXx
4, 5, 24, 25, 32, 33,
34, 35, 42, 43, 44,
45
6
PVINx
SYNC
7 M/S
8 ZAP
9 TDI
10 TDO
11 PGOOD
* Heatsink available in R48.B package
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DESCRIPTION
These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins
directly to the ground plane. These pins should also connect to the negative terminals of the input and output
capacitors. Locate the input and output capacitors as close as possible to the IC.
These pins are the outputs of the corresponding internal power blocks and should be connected to the output
filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize
voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The
Schottky diode should be located as close as possible to the IC.
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly
to PGNDx with ceramic capacitors located as close as possible to the IC.
This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the
SYNC input of another ISL70001ASEH. When configured as an input (Slave Mode), this pin accepts the SYNC
output from another ISL70001ASEH or an external clock. Synchronization of the slave unit is 180° out-of-phase
with respect to the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the
frequency must be within the range of 1MHz ±20%.
This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For SYNC = Output
(Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND.
This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.
This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.
This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.
This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output
voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,
independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin
to DGND with a 10nF ceramic capacitor to mitigate SEE.
3 FN8365.0
May 22, 2013
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ISL70001ASEH
Pin Descriptions (Continued)
PIN NUMBER
12
13, 14
15, 16
17, 18
19
20
21
22
23
PIN NAME
SS
DVDD
DGND
AGND
AVDD
REF
FB
EN
PORSEL
HEATSINK
DESCRIPTION
This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output
ramp time in accordance with Equation 1:
tSS = CSS VREF ISS
(EQ. 1)
where:
tSS = Soft-start output ramp time
CSS = Soft-start capacitor
VREF = Reference voltage (0.6V typical)
ISS = Soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the
IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter
components as close as possible to the IC.
These pins are the digital ground associated with the internal digital control circuitry. Connect these pins
directly to the ground plane.
These pins are the analog ground associated with the internal analog control circuitry. Connect these pins
directly to the ground plane.
This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω
resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC.
This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor
located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or
sinking) is available from this pin.
This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and
from FB to AGND to adjust the output voltage in accordance with Equation 2:
VOUT = VREF ⋅ [1 + (RT RB)]
(EQ. 2)
where:
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VOUT = Output voltage
VREF = Reference voltage (0.6V typical)
RT = Top divider resistor (Must be 1kΩ)
RB = Bottom divider resistor
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE
and to improve stability margins.
This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and
programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF
ceramic capacitor to mitigate SEE.
This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V
supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply
voltages between 5V and 3.3V, connect this pin to DGND.
The heatsink is electrically isolated and should be connected to a thermal chassis of any potential which offers
optimal thermal relief.
4 FN8365.0
May 22, 2013
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ISL70001ASEH
Typical Application Schematic
PVIN1
5V
PVIN2
100µF
1µF
PVIN3
PVIN4
PVIN5
1µF
PVIN6
1 AVDD
1
VSENSE
1µF
1µF
AGND
DVDD
DGND
EN
10nF
M/S
PORSEL
TDI
TDO
ZAP
ISL70001ASEH
http://www.DataSheet4U.net/
LX1
LX2
LX3
LX4
LX5
1µH
LX6
20V
3A
FB
0V TO 5.5V
470µF
1k
1.8V
6A
499
PGOOD
10nF
SYNC
REF
220nF
SS
100nF
FIGURE 3. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION
5 FN8365.0
May 22, 2013
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