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DATASHEET
ISL70001ASEH
Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator
FN8365
Rev 3.00
Aug 8, 2018
The ISL70001ASEH is a radiation hardened and SEE
hardened high-efficiency monolithic synchronous buck
regulator with integrated MOSFETs. This single chip power
solution operates over an input voltage range of 3V to 5.5V
and provides a tightly regulated output voltage that is
externally adjustable from 0.8V to ~85% of the input voltage.
Output load current capacity is 6A for TJ < +145°C.
The ISL70001ASEH utilizes peak current-mode control for
excellent output load transient response and features
integrated compensation and switches at a fixed frequency of
1MHz to reduce component size and count. In application
where two POLs are needed, two ISL70001ASEH devices can
be synchronized 180° out-of-phase to reduce the overall input
RMS ripple current. The internal synchronous power switches
are optimized for high efficiency and good thermal
performance.
The ISL70001ASEH incorporates fault protection for the
regulator. The protection circuits include input undervoltage,
output undervoltage, and output overcurrent.
High integration and class leading radiation tolerance makes
the ISL70001ASEH an ideal choice to power many of today’s
small form factor applications. Two devices can be
synchronized to provide a complete power solution for large
scale digital ICs, like field programmable gate arrays
(FPGAs), that require separate core and I/O voltages.
Applications
• FPGA, CPLD, DSP, CPU Core or I/O voltages
• Low-voltage, high-density distributed power systems
Related Literature
For a full list of related documents, visit our website
ISL70001ASEH product page
Features
• ±1% reference voltage over line, load, temperature and
radiation
• Current mode control for excellent dynamic response
• Full mil-temp range operation (TA = -55°C to +125°C)
• 50% lower shutdown supply current than the ISL70001SEH
• Available in a thermally enhanced heatsink package - R48.B
• Highly efficient: 94% peak efficiency
• Operates from 3V to 5.5V supply
• Adjustable output voltage
- Two external resistors set VOUT from 0.8V to ~85% of VIN
• Bidirectional SYNC pin allows two devices to be
synchronized 180° out-of-phase
• Power-good output voltage monitor
• Adjustable analog soft-start
• Input undervoltage, output undervoltage and output
overcurrent protection
• Electrically screened to DLA SMD 5962-09225
• QML qualified per MIL-PRF-38535 requirements
• Radiation hardness
- Total dose [50-300rad(Si)/s] . . . . . . . . . . . . . . 100krad(Si)
- Total dose [<10mrad(Si)/s] . . . . . . . . . . . . . . 100krad(Si)*
* Product capability established by initial characterization. The
EH version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
• SEE hardness
- SEL and SEB LETeff . . . . . . . . . . . . 86.4MeV/mg/cm2 min
-
SEFI
....
X-section
........
(LETeff =
........
86.4MeV/mg/cm2)
. . . . . . . . . . . . .1.4 x 10-6
cm2
max
- SET LETeff (< 1 pulse perturbation) 86.4MeV/mg/cm2 min
5V Supply
ISL70001ASEH
SYNCH
ISL75051SEH
CORE
AUX
RAD TOLERANT
FPGA
ISL70001ASEH
SYNCH
I/O
FIGURE 1. TYPICAL APPLICATION
100
95
90
85
1.5V
1.8V
80
2.5V
3.3V
1.2V
75
70
012345
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY 5V INPUT, TA = +25°C
6
FN8365 Rev 3.00
Aug 8, 2018
Page 1 of 26

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ISL70001ASEH
Functional Block Diagram
PORSEL
EN
POWER-ON
RESET (POR)
SS
FB
PGOOD
REF
SYNC
M/S
SOFT
START
SLOPE
COMPENSATION
EA GM
PWM
CONTROL
LOGIC
COMPENSATION
CURRENT
SENSE
GATE
DRIVE
UV
POWER-GOOD
PWM
REFERENCE
0.6V
BIT
TRIM
PGNDx
AGND
DGND
AVDD
DVDD
PVINx
LXx
PGNDx
TDI
TDO
ZAP
PGNDx
FN8365 Rev 3.00
Aug 8, 2018
Page 2 of 26

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ISL70001ASEH
Ordering Information
ORDERING SMD NUMBER
(Note 1)
PART NUMBER
(Note 2)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962R0922503VXC
ISL70001ASEHVF
-55 to +125 48 Ld CQFP
R48.A
5962R0922503VYC
ISL70001ASEHVFE
-55 to +125 48 Ld CQFP with Heatsink
R48.B
5962R0922503V9A
ISL70001ASEHVX
-55 to +125 Die
N/A
ISL70001ASEHF/PROTO (Note 3)
-55 to +125 48 Ld CQFP
R48.A
N/A
ISL70001ASEHFE/PROTO (Note 3)
-55 to +125 48 Ld CQFP with Heatsink
R48.B
N/A
ISL70001ASEHX/SAMPLE (Note 3)
-55 to +125 Die
N/A
ISL70001ASEHEV1Z (Note 4)
Evaluation Board
NOTES:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
Ordering Information table must be used when ordering.
2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations.
3. The /PROTO and /SAMPLE (Die) have no traceability and are intended for engineering evaluation purposes only. The /PROTO part meets the electrical
limits and conditions across temperature (-55°C to +125°C) specified in the datasheet or DLA SMD and is in the same form and fit as the flight
devices (Class V parts). The SAMPLE die is capable of meeting the electrical limits and conditions specified in the data sheet or DLA SMD. The
/SAMPLE is a die and as such, does not receive 100% screening over temperature to the datasheet or DLA SMD requirements so, some level of
fallout should be expected. These part types do not come with a Certificate of Conformance because there is no Radiation Assurance testing or items
such as TCI/QCI, Burn-in, X-ray, SEM, etc.
4. Evaluation board uses the /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity.
FN8365 Rev 3.00
Aug 8, 2018
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ISL70001ASEH
Pin Configuration
ISL70001ASEH
(48 LD CQFP)
TOP VIEW
M/S
ZAP
TDI
TDO
PGOOD
SS
DVDD
DVDD
DGND
DGND
AGND
AGND
6 5 4 3 2 1 48 47 46 45 44 43
7 42
8 41
9 40
10 39
11 38
12 37
13 * HEATSINK 36
14 35
15 34
16 33
17 32
1819
20
21
22
23
24
25
26
27
28
29
31
30
PVIN3
LX3
PGND3
PGND3
PGND4
PGND4
LX4
PVIN4
PVIN4
PVIN5
PVIN5
LX5
* Heatsink available in R48.B package
Pin Descriptions
PIN NUMBER PIN NAME
DESCRIPTION
1, 2, 27, 28, 29,
30, 37, 38, 39, 40,
47, 48
PGNDx
These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins
directly to the ground plane. These pins should also connect to the negative terminals of the input and output
capacitors. Locate the input and output capacitors as close as possible to the IC.
3, 26, 31, 36, 41,
46
LXx These pins are the outputs of the corresponding internal power blocks and should be connected to the output filter
inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize voltage
undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The Schottky diode
should be located as close as possible to the IC.
4, 5, 24, 25, 32,
33, 34, 35, 42, 43,
44, 45
PVINx
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be connected to
a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly to PGNDx with
ceramic capacitors located as close as possible to the IC.
6 SYNC This pin is the synchronization I/O for the IC. When configured as an output (Master Mode), this pin drives the SYNC
input of another ISL70001ASEH. When configured as an input (Slave Mode), this pin accepts the SYNC output from
another ISL70001ASEH or an external clock. Synchronization of the slave unit is 180° out-of-phase with respect to
the master unit. If synchronizing to an external clock, the clock must be SEE hardened and the frequency must be
within the range of 1MHz ±20%.
7 M/S This pin is the Master/Slave input for selecting the direction of the bidirectional SYNC pin. For SYNC = Output (Master
Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to DGND.
8 ZAP This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.
9 TDI This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.
10 TDO This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.
11 PGOOD This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND when the output voltage
is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V, independent of
the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin to DGND with a 10nF
ceramic capacitor to mitigate SEE.
FN8365 Rev 3.00
Aug 8, 2018
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ISL70001ASEH
Pin Descriptions (Continued)
PIN NUMBER
12
13, 14
15, 16
17, 18
19
20
21
22
23
PIN NAME
DESCRIPTION
SS This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output ramp
time in accordance with Equation 1:
tSS = CSS VREF ISS
(EQ. 1)
where:
tSS = Soft-start output ramp time
CSS = Soft-start capacitor
VREF = Reference voltage (0.6V typical)
ISS = Soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
DVDD
These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the IC and
locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as close
as possible to the IC.
DGND These pins are the digital ground associated with the internal digital control circuitry. Connect these pins directly to
the ground plane.
AGND These pins are the analog ground associated with the internal analog control circuitry. Connect these pins directly to
the ground plane.
AVDD This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω resistor
and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC.
REF This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor located as
close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or sinking) is available
from this pin.
FB This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and from FB
to AGND to adjust the output voltage in accordance with Equation 2:
VOUT = VREF  1 + RT RB
(EQ. 2)
where:
VOUT = Output voltage
VREF = Reference voltage (0.6V typical)
RT = Top divider resistor (Must be 1kΩ)
RB = Bottom divider resistor
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate SEE and to
improve stability margins.
EN This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and programmable
hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF ceramic capacitor to
mitigate SEE.
PORSEL This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V supply,
connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply voltages between
5V and 3.3V, connect this pin to DGND.
HEATSINK The heatsink is electrically isolated and should be connected to a thermal chassis of any potential which offers optimal
thermal relief.
FN8365 Rev 3.00
Aug 8, 2018
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