Pin Functional Description
DRAIN (D) Pin:
Power MOSFET Drain connection. Provides internal operating
current for both start-up and steady-state operation.
BYPASS (BP) Pin:
Connection point for a 0.1 mF external bypass capacitor for the
internally generated 5.8 V supply.
FEEDBACK (FB) Pin:
During normal operation, switching of the power MOSFET is
controlled by this pin. Power MOSFET switching is terminated
when a current greater than 49 µA is delivered into this pin.
SOURCE (S) Pin:
This pin is the power MOSFET source connection. It is also the
ground reference for the BYPASS and FEEDBACK pins.
P Package (PDIP-8B) D Package (SO-8C)
Figure 4. Pin Configuration.
LYTSwitch-0 Functional Description
LYTSwitch-0 combines a high-voltage power MOSFET switch
with a power supply controller in one device. Unlike conventional
PWM (pulse width modulator) controllers, LYTSwitch-0 uses a
simple ON/OFF control to regulate the output voltage. The
LYTSwitch-0 controller consists of an oscillator, feedback (sense
and logic) circuit, 5.8 V regulator, BYPASS pin undervoltage circuit,
over-temperature protection, frequency jittering, current limit
circuit, leading edge blanking and a 700 V power MOSFET. The
LYTSwitch-0 incorporates additional circuitry for auto-restart.
The typical oscillator frequency is internally set to an average of
66 kHz. Two signals are generated from the oscillator: the
mindaixciamteusmthdeutbyecgyincnleinsgigonfael a(DchCMcAyXc)lae.nd the clock signal that
The LYTSwitch-0 oscillator incorporates circuitry that introduces
a small amount of frequency jitter, typically 4 kHz peak-to-peak,
to minimize EMI emission. The modulation rate of the frequency
jitter is set to 1 kHz to optimize EMI reduction for both average
and quasi-peak emissions. The frequency jitter should be
measured with the oscilloscope triggered at the falling edge of
the Drain waveform. The waveform in Figure 5 illustrates the
frequency jitter of the LYTSwitch-0.
Feedback Input Circuit
The feedback input circuit at the FEEDBACK pin consists of a
low impedance source follower output set at 1.65 V. When the
current delivered into this pin exceeds 49 µA, a low logic level
(disable) is generated at the output of the feedback circuit. This
output is sampled at the beginning of each cycle on the rising
edge of the clock signal. If high, the power MOSFET is turned
on for that cycle (enabled), otherwise the power MOSFET remains
off (disabled). Since the sampling is done only at the beginning
of each cycle, subsequent changes in the FEEDBACK pin
voltage or current during the remainder of the cycle are ignored.
5.8 V Regulator and 6.3 V Shunt Voltage Clamp
The 5.8 V regulator charges the bypass capacitor connected to
the BYPASS pin to 5.8 V by drawing a current from the voltage
on the DRAIN, whenever the power MOSFET is off. The BYPASS
pin is the internal supply voltage node for the LYTSwitch-0.
When the power MOSFET is on, the LYTSwitch-0 runs off of the
energy stored in the bypass capacitor. Extremely low power
consumption of the internal circuitry allows the LYTSwitch-0 to
operate continuously from the current drawn from the DRAIN
pin. A bypass capacitor value of 0.1 µF is sufficient for both
high frequency decoupling and energy storage.
BYPASS Pin Undervoltage
The BYPASS pin undervoltage circuitry disables the power
MOSFET when the BYPASS pin voltage drops below 4.85 V.
Once the BYPASS pin voltage drops below 4.85 V, it must rise
back to 5.8 V to enable (turn-on) the power MOSFET.
The thermal shutdown circuitry senses the die temperature.
The threshold is set at 142 °C typical with a 75 °C hysteresis.
When the die temperature rises above this threshold (142 °C)
the power MOSFET is disabled and remains disabled until the
die temperature falls by 75 °C, at which point it is re-enabled.
The current limit circuit senses the current in the power
MOSFET. When this current exceeds the internal threshold
(ILIMIT), the power MOSFET is turned off for the remainder of that
cycle. The leading edge blanking circuit inhibits the current limit
comparator for a short time (tLEB) after the power MOSFET is
turned on. This leading edge blanking time has been set so
that current spikes caused by capacitance and rectifier reverse
recovery time will not cause premature termination of the
switching pulse cycle.
In the event of a fault condition such as output overload, output
short, or an open loop condition, LYTSwitch-0 enters into
auto-restart operation. An internal counter clocked by the
oscillator gets reset every time the FEEDBACK pin is pulled
Rev. B 06/15