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www.fairchildsemi.com
FAN5018B
6-Bit VID Controller 2-4 Phase VR10.X Controller
Features
• Improved Noise Immunity
• Improved Load Line Accuracy
• TTL Compatible VID Inputs
• Fully Pin and Function compatible with existing
FAN5018 and ADP3180 Controllers
• Precision Multi-Phase DC-DC Core Voltage Regulation
– ±14mV Output Voltage Accuracy Over Temperature
• Differential Remote Voltage Sensing
• Selectable 2-, 3-, or 4-Phase Operation
• Selectable VRM9 or VRM10 Operation
• Up to 1MHz per Phase Operation (4MHz ripple
Frequency)
• Lossless Inductor Current Sensing for Loadline
Compensation
– External Temperature Compensation
• Accurate Loadline Programming (Meets Intel®
VRM/VRD10.x CPU Specifications)
• Accurate Channel-Current Balancing for Thermal
Optimization and Layout Compensation
• Convenient 12V Supply Biasing
• 6-bit Voltage Identification (VID) Input
– .8375V to 1.600V in 12.5mV Steps
– Dynamic VID Capability with Fault-Blanking for
glitch-less Output voltage Changes
• Adjustable Over Current Protection with Programmable
Latch-Off Delay. Latch-Off Function may be Disabled
• Over-Voltage Protection – Internal OVP Crowbar
Protection
• Package: 28L-TSSOP
Applications
• VRM/VRD 9.x and 10.x Computer DC/DC Converter
• High-Current, Low-Voltage DC/DC Rail
General Description
The FAN5018B is a multi-phase DC-DC controller for
implementing high-current, low-voltage, CPU core power
regulation circuits. It is part of a chipset that includes exter-
nal MOSFET drivers and power MOSFETS. The
FAN5018B drives up to four synchronous-rectified buck
channels in parallel. The multi-phase buck converter archi-
tecture uses interleaved switching to multiply ripple fre-
quency by the number of phases and reduce input and output
ripple currents. Lower ripple results in fewer components,
lower component cost, reduced power dissipation, and
smaller board area.
The FAN5018B features a high-bandwidth control loop to
provide optimal response to load transients. The FAN5018B
senses current using lossless techniques: Phase current is
measured through each of the output inductors. This current
information is summed, averaged and used to set the loadline
of the output via programmable "droop." The droop is tem-
perature compensated to achieve precise loadline character-
istics over the entire operating range. Additionally,
individual phase current is measured using the RDS(ON) of
the low-side MOSFETs. This information is used to dynam-
ically balance/steer per-phase current. The phase currents
are also summed and averaged for over-current detection.
Dynamic-VID technology allows on-the-fly VID changes
with controlled, glitch-less output. Additionally, short-circuit
protection, adjustable current limiting, over-voltage protec-
tion and power-good circuitry combine to ensure reliable and
safe operation. FAN5018B is specified over the commercial
temperature range of 0°C to +85°C and operates from a sin-
gle +12V supply which simplifies design. FAN5018B is
available in a 28L-TSSOP package.
Block Diagram
VIN
Φ1 FAN5009
Φ2
FAN5018B
Φ3
Φ4 FAN5009
VIN
VOUT
REV. 1.0.0 Jul/15/05
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FAN5018B
Pin Assignments
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
VID5/SEL 6
FBRTN 7
FB 8
COMP 9
PWRGD 10
EN 11
DELAY 12
RT 13
RAMPADJ 14
FAN5018B
TSSOP-28
28 VCC
27 PWM1
26 PWM2
25 PWM3
24 PWM4
23 SW1
22 SW2
21 SW3
20 SW4
19 GND
18 CSCOMP
17 CSSUM
16 CSREF
15 ILIMIT
PRODUCT SPECIFICATION
Pin Definitions
Pin Number
1–5
6
Pin Name
VID [4:0]
VID5/SEL
Pin Function Description
VID inputs. Determines the output voltage via the internal DAC. These inputs
comply to VRM10/VRD10 specifications for static and dynamic operation. All have
internal pull-ups (1.25V for VRM10 and 2.5V for VRM9) so leaving them open
results in logic high. Leaving VID[4:0] open results in a "No CPU" condition
disabling the PWM outputs.
VID5 Input/DAC Select. Dual function pin that is either the 12.5mV DAC LSB for
VRM10 or selects the VRM9 DAC codes when forced higher than Vtblsel(VRM9)
voltage. The truth table is as follows:
VVID5/SEL held > Vtblsel(VRM9); VRM9 DAC table is selected (See Table 3)
VViD5/SEL < Vtblsel(VRM10); VRM10 DAC table is selected (See Table 2) and
VViD5/SEL pin is used as VID5 input.
7 FBRTN Feedback Return. Error Amp and DAC reference point.
8 FB Feedback Input. Inverting input for Error Amp this pin is used for external
compensation. This pin can also be used to introduce DC offset voltage to the
output.
9 COMP Error Amp output. This pin is used for external compensation.
10 PWRGD Power Good output. This is an open-drain output that asserts when the output
voltage is within the specified tolerance. It is expected to be pulled up to an external
voltage rail.
11 EN Enable. Logic signal that enables the controller when logic high.
12 DELAY Soft-start and Current Limit Delay. An external resistor and capacitor sets the
softstart ramp rate and the over-current latch off delay.
13 RT Switching Frequency Adjust. This pin adjusts the output PWM switching
frequency via an external resistor.
14 RAMPADJ PWM Current Ramp Adjust. An external resistor to Vcc will adjust the amplitude of
the internal PWM ramp.
15 ILIMIT Current Limit Adjust. An external resistor sets the current limit threshold for the
regulator circuit. This pin is internally pulled low when EN is low or the UVLO circuit
is active. It is also used to enable the drivers.
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PRODUCT SPECIFICATION
FAN5018B
Pin Definitions (continued)
Pin Number
16
17
18
19
20–23
24–27
28
Pin Name
CSREF
CSSUM
CSCOMP
GND
SW[4:1]
PWM[4:1]
VCC
Pin Function Description
Current Sense Reference. Non-Inverting input of the current sense amp. Sense
point for the output voltage used for OVP and PWRGD.
Current Sense Summing node. Inverting input of the current sense amp.
Current Sense Compensation node. Output of the current sense amplifier. This
pin is used, in conjunction with CSSUM to set the output droop compensation and
current loop response.
Ground. Signal ground for the device.
Phase Current Sense/Balance inputs. Phase-to-phase current sense and
balancing inputs. Unused phases should be left open.
PWM outputs. CMOS outputs for driving external gate driver such as the FAN5009.
Unused phases should be connected to Ground.
Chip Power. Bias supply for the chip. Connect directly to a +12V supply. Bypass
with a 1µF MLCC capacitor.
REV. 1.0.0 Jul/15/05
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FAN5018B
PRODUCT SPECIFICATION
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Func-
tional operation under these conditions is not implied.
Parameter
Min.
Max.
Units
Supply Voltage: VCC to GND
-0.3 +15
V
Voltage on FBRTN pin
-0.3 +0.3
V
Voltage on SW1-SW4 (<250ns duration)
-5 +25 V
Voltage on SW1-SW4 (>=250ns duration)
-0.3 +15
V
Voltage on RAMPADJ, CSSUM
-0.3 VCC+0.3
V
Voltage on any other pin
-0.3 +5.5
V
Thermal Information
Parameter
Operating Junction Temperature (TJ)
Storage Temperature
Lead Soldering Temperature, 10 seconds
Vapor Phase, 60 seconds
Infrared, 15 seconds
Power Dissipation (PD) @ TA = 25°C
Thermal Resistance (θJA) (See Note 1)
Min. Typ Max. Units
0 +150 °C
–65 +150 °C
+300 °C
+215 °C
+220 °C
2W
50 °C/W
Recommended Operating Conditions (See Figure 8)
Parameter
Supply Voltage VCC
Ambient Operating Temperature
Operating Junction Temperature (TJ)
Note:
1: θJA is defined as 1 oz. copper PCB with 1 in2 pad.
Conditions
VCC to GND
Min.
10.2
0
0
Typ.
12
Max.
13.8
+85
+125
Units
V
°C
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PRODUCT SPECIFICATION
FAN5018B
Electrical Specifications
(VCC = 12V, TA = 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The denotes specifications which apply over the full operating temperature range.
Parameter
Error Amplifier
Output Voltage Range
Accuracy
Symbol
VCOMP
VFB
Line Regulation
Input Bias Current
FBRTN Current
Output Current
Gain Bandwidth Product
DC Gain
VID Inputs
Input Low Voltage
ΔVFB
IFB
IFBRTN
IO(ERR)
GBW
VIL(VID)
Input High Voltage
VIH(VID)
Input Current, VID Low
Input Current, VID High
Pull-up Resistance
Internal Pull-up Voltage
IIL(VID)
IIH(VID)
RVID
VID Transition Delay
Time2
“No CPU” Detection
Turn-off Delay Time2
VID Table Select
Vtblsel
Oscillator
Frequency
Frequency Variation
fOSC
fPHASE
Output Voltage
RAMPADJ Pin Accuracy
VRT
VRAMPADJ
RAMPADJ Input Current
Current Sense Amplifier
Offset Voltage
Input Bias Current
Gain Bandwidth Product
IRAMPADJ
VOS(CSA)
IBIAS(CSA)
GBW
Conditions
Min. Typ. Max. Units
0.5
3.5
Relative to DAC Setting,
referenced to FBRTN,
CSSUM = CSCOMP,
Test Circuit 3
VRM10 -14
VRM9 -17
+14
+17
VCC=10V to 14V
0.05
-17 -15 -13
150 180
FB forced to VOUT – 3%
300 500
COMP = FB ( See Note 2)
20
CCOMP = 10pF ( See Note 2)
77
V
mV
%
µA
µA
µA
MHz
dB
VRM10
VRM9
VRM10
VRM9
VID(X) = 0V
VID(X) = 1.15V
Internal
VRM10
VRM9
VID Code Change to FB Change
0.4
0.8
0.8
2.0
-30 -20
-2
2
35
60 115
1.0 1.15 1.26
2.2 2.4 2.6
400
VID Code Change to 11111X to PWM
going low
To select VRM9 table
To select VRM10 table (becomes VID5)
400
4
3.5
V
V
V
V
µA
µA
kΩ
V
V
ns
ns
V
V
TA = +25°C, RT = 250kΩ, 4-Phase
TA = +25°C, RT = 115kΩ, 4-Phase
TA = +25°C, RT = 75kΩ, 4-Phase
RT = 100kΩ to GND
VRAMPADJ = Vdac = +2K • (Vin–Vdac)/
(Rr+2k) @ 20µA
Current into RAMPADJ pin
200
4000
155 200 245
400
600
1.9 2.0 2.1
-50
+50
0 100
kHz
kHz
kHz
kHz
V
mV
µA
CSSUM–CSREF, Test Circuit 1
COMP = FB ( See Note 2)
-3.0
+3.0 mV
-50
+50 nA
10 MHz
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
REV. 1.0.0 Jul/15/05
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