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Data Sheet
July 29, 2005
X45620
FN8250.0
Dual Voltage Monitor with Integrated
System Battery Switch and EEPROM
FEATURES
• Dual voltage monitoring
• Active low reset outputs
• Two standard reset threshold voltages
—Factory programmable threshold
• Lowline Output — zero delayed POR
• Reset signal valid to VCC = 1V
• System battery switch-over circuitry
• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)
• 256Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
programmable Block Lockprotection
—In circuit programmable ROM mode
• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 400kHz 2-wire Interface
BLOCK DIAGRAM
• 2.7V to 5.5V power supply operation
• Available package — 20-lead TSSOP
• Dual supervisor
• Battery switch and output
DESCRIPTION
The Intersil X45620 combines power-on reset control,
battery switch circuit, watchdog timer, supply voltage
supervision, secondary voltage supervision, block lock
protect and serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to
stabilize before the processor can execute code.
A system battery switch circuit compares VCC (V1MON)
with VBATT input and connects VOUT to whichever is
higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X45620
can drive 50mA from VCC and 250µA from VBATT. The
device switches to VBATT when VCC drops below the
low VCC voltage threshold and VBATT > VCC.
V2MON
WP
SDA
SCL
S0
S1
VCC
(V1MON)
VOUT
VBATT
V2 Monitor
Logic
VOUT
+
VTRIP2
-
Watchdog Transition
Detector
Data
Register
Command
Decode, Test
& Control
Logic
Device
Select
Logic
System
Battery
Switch
VCC Monitor
Logic
Protect Logic
Status
Register
EEPROM
Array
512 X 512
(32K X 8 Bit)
VOUT
+
VTRIP1
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on,
Low Voltage
Reset
Generation
V2FAIL
WDO
BATT-ON
RESET/MR
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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X45620
DESCRIPTION (Continued)
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC (V1MON) falls below the mini-
mum VCC trip point (VTRIP1). RESET is asserted until
VCC returns to proper operating level and stabilizes. A
second voltage monitor circuit tracks the unregulated
supply or monitors a second power supply voltage to
provide a power fail warning. Intersil’s unique circuits
allow the threshold for either voltage monitor to be
reprogrammed to meet special needs or to fine-tune
the threshold for applications requiring higher preci-
sion. (Contact factory for custom VTRIP options)
PIN CONFIGURATION
20-Pin TSSOP
S0
S1
NC
LOWLINE
NC
V2FAIL
V2MON
RESET/MR
WDO
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC (V1MON)
WP
NC
BATT-ON
VOUT
VBATT
SCL
NC
NC
SDA
Ordering Information
VCC Range
4.75–5.5V
VTRIP1 Range
4.5–4.75V
2.7–5.5V
2.55–2.7V
VTRIP2 Range
2.55–2.7V
1.7–1.80V
Package
20L TSSOP
20L TSSOP
Operating
Temperature Range
0°C–70°C
-40°C–85°C
0°C–70°C
-40°C–85°C
Part Number
X45620V20
X45620V20I
X45620V20-2.7
X45620V20I-2.7
PIN DESCRIPTION
Pin Name
Function
1 S0 Device Select Input. This pin has an internal pull down resistor. (>10Mtypical)
2 S1 Device Select Input. This pin has an internal pull down resistor. (>10Mtypical)
3 NC No internal connections
4 LOWLINE Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1 and immediately
goes HIGH when VCC > VTRIP1.
5 NC No internal connections
6 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
7 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or VCC
when not used.
2 FN8250.0
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X45620
PIN DESCRIPTION (Continued)
Pin Name
8 RESET
/MR
9 WDO
10 VSS
11 SDA
14
12–13
15
SCL
NC
VBATT
16 VOUT
17 BATT-ON
18 NC
19 WP
20 VCC
(V1MON)
Function
Reset Output/Manual Reset Input. This is an Input/Output pin.
RESET Output. This is an active LOW, open drain output which goes active whenever VCC falls
below the minimum VCC sense level. When RESET is active communication to the device is interrupt-
ed. RESET remains active until VCC rises above the minimum VCC sense level for tPURST. RESET
also goes active on power-up and remains active for tPURST after the power supply stabilizes.
MR Input. This is an active LOW debounced input. When MR is active, the RESET pins are assert-
ed. When MR is released, the RESET remains asserted for tPURST, and then released.
Watchdog Output. WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It is an open
drain output, requires the use of a pull-up resistor.
Serial Clock. The SCL input is used to clock all data into and out of the device.
No internal connections
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
mary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused, connect VBATT
to ground.
Output Voltage.
VOUT = VCC if VCC > VTRIP1.
IF VCC < VTRIP1, then,
VOUT = VCC if VCC > VBATT+0.03
VOUT = VBATT if VCC < VBATT-0.03
Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW
when VOUT switches to VCC. It is used to drive a external P-channel FET when VCC = VOUT and
current requirements are greater than 50mA.
The purpose of this output is to drive an external FET to get higher operating currents when the
VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the
VOUT pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data-there is no
communication at this time.
No Connect
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits. This pin has an internal pull down
resistor. (>10Mtypical)
Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
voltage, RESET and LOWLINE go ACTIVE.
3 FN8250.0
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X45620
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with
respect to VSS ...................................... -1.0V to +6V
D.C. output current
(all output pins except VOUT)............................. 5mA
D.C. output current VOUT.................................... 50mA
Lead temperature (soldering, 10 seconds) ........ 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min
0°C
-40°C
Max
70°C
+85°C
Device Option
-2.7
Blank
Supply Voltage
2.7V-5.5V
4.75V-5.5V
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified)
Symbol
ICC1
ICC2
ICC3
IBATT1
IBATT2
VOUT1
VOUT2
VOLB
VBSH
VTRIP1
VTRIP2
Parameter
VCC Supply Current (Active)
(Excludes IOUT) Read Memory array
(Excludes IOUT) Write nonvolatile
Memory
VCC Supply Current (Passive)
(Excludes IOUT)
VCC Current (Battery Backup Mode)
(Excludes IOUT)
VBATT Current (Excludes IOUT)
VBATT Current (Excludes IOUT)
(Battery Backup Mode)
Output Voltage (VCC > VBATT + 0.03V or
VCC > VTRIP1
Output Voltage (VCC < VBATT + 0.03V
and VCC < VTRIP1) {Battery Backup}
Output (BATT-ON) LOW Voltage
Battery Switch Hysteresis
(VCC < VTRIP1)
VCC Reset Trip Point Voltage
V2MON Reset Trip Point Voltage
Limits
Min Typ (6) Max Unit Test Conditions
mA SCL = 400kHz
1.5 VOUT, RESET,
3.0 LOWLINE = Open
Note 1
µA SDA = VCC, Any Input =
50 VSS or VCC: VOUT,
RESET, LOWLINE =
Open, Note 2
1 µA VBATT = 2.8V, VOUT, RE-
SET = Open, Note 4, 1
1 µA VOUT = VCC, Note 4
50 µA VOUT = VBATT,
VBATT = 2.8V
VOUT, RESET = Open,
Note 4
VCC – 0.05
VCC – 0.5
VBATT – 0.2
VCC – 0.02
VCC – 0.2
V
V
V
IOUT = -5mA
IOUT = -50mA
IOUT = -250µA
4.5
2.55
2.55
1.7
4.62
2.62
2.62
1.75
0.4
30
-30
4.75
2.7
2.7
1.8
V IOL = 3.0mA (5V)
IOL = 1.0mA (3V)
mV Power-up
mV Power-down, Note 4
V X45620
X45620-2.7
V X45620
X45620-2.7
4 FN8250.0
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X45620
D.C. OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions unless otherwise specified)
Symbol
VOLR
Parameter
Output (RESET, LOWLINE, WDO,
V2FAIL) LOW Voltage
Two Wire Interface
VIL
VIH
ILI
VOLS
Input (SDA, S0, S1, SCL, WP) LOW
Voltage
Input (SDA, S0, S1, SCL, WP) HIGH
Voltage
Input Leakage Current (SDA, S1, S0,
SCL, WP)
Output (SDA) LOW Voltage
Limits
Min Typ (6) Max Unit Test Conditions
0.4 V IOL = 3.0mA (5V)
IOL = 1.0mA (3V)
-0.5
VCC x 0.7
VCC x 0.3 V Note 3
VCC + 0.5 V Note 3
±10 µA
0.4 V IOL = 3.0mA (5V)
IOL = 1.0mA (3V), Note 4
Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL min. and VIH max. are for reference only and are not tested.
(4) This parameter is guaranteed by characterization.
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Test
COUT Output Capacitance (SDA, RESET, V2FAIL, LOWLINE, BATT-ON, WDO)
CIN Input Capacitance (SDA, SCL, S0, S1, WP)
Max
8
6
Unit
pF
pF
Conditions
VOUT = 0V,
Note 1, 4
VIN = 0V,
Note 1, 4
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
VCC
VCC
1.53k
1.53k
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
SDA
RESET
V2FAIL
LOWLINE
WDO
BATT-ON
30pF
30pF 4481
5 FN8250.0
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