K4B2G1646B.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 K4B2G1646B 데이타시트 다운로드

No Preview Available !

Rev. 1.41, Nov. 2010
K4B2G0446B
K4B2G0846B
K4B2G1646B
2Gb B-die DDR3 SDRAM
78 / 96 FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
Free Datasheet http://www.datasheet4u.com/

No Preview Available !

K4B2G0446B
K4B2G0846B
K4B2G1646B
datasheet
Revision History
Revision No.
1.0
1.1
1.2
1.3
1.4
1.41
History
- First Release
- ADD IDDQ2NT, IDDQ4R, IDD8 Specification
- Corrected AC Timing Table & Typo.
- Added IDD Current Specification for DDR3-1600 (x4/x8) & Cor-
rected Typo.
- Added Layout and Corrected Typo.
- Corrected typo.
Draft Date
Dec. 2008
Jul. 2009
Sep. 2009
Oct. 2009
Nov. 2009
Nov. 2010
Rev. 1.41
DDR3 SDRAM
Remark
-
-
-
-
-
-
Editor
S.H.KiM
S.H.KiM
S.H.KiM
S.H.KiM
S.H.KiM
S.H.KiM
-2-
Free Datasheet http://www.datasheet4u.com/

No Preview Available !

K4B2G0446B
K4B2G0846B
K4B2G1646B
datasheet
Rev. 1.41
DDR3 SDRAM
Table Of Contents
2Gb B-die DDR3 SDRAM
1. Ordering Information ..................................................................................................................................................... 5
2. Key Features................................................................................................................................................................. 5
3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6
3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6
3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7
3.3 x16 Package Pinout (Top view) : 96ball FBGA Package ........................................................................................ 8
3.4 FBGA Package Dimension (x4/x8) .......................................................................................................................... 9
3.5 FBGA Package Dimension (x16)............................................................................................................................. 10
4. Input/Output Functional Description.............................................................................................................................. 11
5. DDR3 SDRAM Addressing ........................................................................................................................................... 12
6. Absolute Maximum Ratings .......................................................................................................................................... 13
6.1 Absolute Maximum DC Ratings............................................................................................................................... 13
6.2 DRAM Component Operating Temperature Range ................................................................................................ 13
7. AC & DC Operating Conditions..................................................................................................................................... 13
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 13
8. AC & DC Input Measurement Levels ............................................................................................................................ 14
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 14
8.2 VREF Tolerances...................................................................................................................................................... 15
8.3 AC & DC Logic Input Levels for Differential Signals ............................................................................................... 16
8.3.1. Differential signals definition ............................................................................................................................ 16
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 16
8.3.3. Single-ended requirements for differential signals ........................................................................................... 17
8.4 Differential Input Cross Point Voltage...................................................................................................................... 18
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 18
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 18
9. AC & DC Output Measurement Levels ......................................................................................................................... 19
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 19
9.2 Differential AC & DC Output Levels......................................................................................................................... 19
9.3 Single-ended Output Slew Rate .............................................................................................................................. 19
9.4 Differential Output Slew Rate .................................................................................................................................. 20
9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 20
9.6 Overshoot/Undershoot Specification ....................................................................................................................... 21
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 21
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 21
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 22
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 23
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 23
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 24
9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 25
9.9 ODT Timing Definitions ........................................................................................................................................... 26
9.9.1. Test Load for ODT Timings .............................................................................................................................. 26
9.9.2. ODT Timing Definitions .................................................................................................................................... 26
10. IDD Current Measure Method..................................................................................................................................... 29
10.1 IDD Measurement Conditions ............................................................................................................................... 29
11. 2Gb DDR3 SDRAM B-die IDD Specification Table .................................................................................................... 38
12. Input/Output Capacitance ........................................................................................................................................... 40
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 ...................................................................... 41
13.1 Clock Specification ................................................................................................................................................ 41
13.1.1. Definition for tCK(avg).................................................................................................................................... 41
13.1.2. Definition for tCK(abs).................................................................................................................................... 41
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 41
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 41
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 41
13.1.6. Definition for tERR(nper) ................................................................................................................................ 41
-3-
Free Datasheet http://www.datasheet4u.com/

No Preview Available !

K4B2G0446B
K4B2G0846B
K4B2G1646B
datasheet
Rev. 1.41
DDR3 SDRAM
13.2 Refresh Parameters by Device Density................................................................................................................. 42
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 42
13.3.1. Speed Bin Table Notes .................................................................................................................................. 45
14. Timing Parameters by Speed Grade .......................................................................................................................... 46
14.1 Jitter Notes ............................................................................................................................................................ 49
14.2 Timing Parameter Notes........................................................................................................................................ 50
14.3 Address/Command Setup, Hold and Derating : .................................................................................................... 51
14.4 Data Setup, Hold and Slew Rate Derating : .......................................................................................................... 57
-4-
Free Datasheet http://www.datasheet4u.com/

No Preview Available !

K4B2G0446B
K4B2G0846B
K4B2G1646B
datasheet
1. Ordering Information
[ Table 1 ] Samsung 2Gb DDR3 B-die ordering information table
Organization
DDR3-800 (6-6-6)
DDR3-1066 (7-7-7)4
512Mx4
K4B2G0446B-HCF7
K4B2G0446B-HCF8
256Mx8
K4B2G0846B-HCF7
K4B2G0846B-HCF8
128Mx16
K4B2G1646B-HCF7
K4B2G1646B-HCF8
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. Backward Compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7), DDR3-800(6-6-6)
3. Backward Compatible to DDR3-1066(7-7-7), DDR3-800(6-6-6)
4. Backward Compatible to DDR3-800(6-6-6)
DDR3-1333 (9-9-9)3
K4B2G0446B-HCH9
K4B2G0846B-HCH9
K4B2G1646B-HCH9
Rev. 1.41
DDR3 SDRAM
DDR3-1600 (11-11-11)2
K4B2G0446B-HCK0
K4B2G0846B-HCK0
K4B2G1646B-HCK0
Package
78 FBGA
78 FBGA
96 FBGA
2. Key Features
[ Table 2 ] 2Gb DDR3 B-die Speed bins
Speed
DDR3-800
6-6-6
tCK(min)
2.5
CAS Latency
6
tRCD(min)
15
tRP(min)
15
tRAS(min)
37.5
tRC(min)
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
DDR3-1600
11-11-11
1.25
11
13.75
13.75
35
48.75
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin,
667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 Banks
• Programmable CAS Latency(posted CAS): 5, 6, 7, 8, 9, 10, 11
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 2Gb DDR3 SDRAM B-die is organized as a 64Mbit x 4 I/Os x 8banks,
32Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchro-
nous device achieves high speed double-data-rate transfer rates of up to
1600Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ.
The 2Gb DDR3 B-die device is available in 78ball FBGAs(x4/x8) and
96balls FBGA(x16).
NOTE : 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
-5-
Free Datasheet http://www.datasheet4u.com/