AD9814S.pdf 데이터시트 (총 7 페이지) - 파일 다운로드 AD9814S 데이타시트 다운로드

No Preview Available !

14-Bit CCD/CIS
Signal Processor
AD9814S
1.0 Scope
This specification documents the detail requirements for space qualified product manufactured on Analog Devices, Inc.'s QML
certified line per MIL-PRF-38535 Level V except as modified herein.
The manufacturing flow described in the STANDARD SPACE LEVEL PRODUCTS PROGRAM brochure is to be considered
a part of this specification. http://www.analog.com/aerospace.
This data sheet specifically details the space grade version of this product. A more detailed operational description and a
complete data sheet for commercial product grades can be found at www.analog.com/AD9814.
2.0 Part Number. The complete part number(s) of this specification follow:
Part Number
AD9814-703F
Description
Complete 14-Bit CCD/CIS Signal Processor
3.0 Case Outline
Letter
Descriptive designator
F CDFP3-F28
Case Outline (Lead Finish per MIL-PRF-38535)
28 lead bottom-brazed flatpack
Figure 1 - Functional Block Diagram
ASD0016515
Rev. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of
their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2010 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/

No Preview Available !

AD9814S
Pin Number
Name
Type
Description
1
CDSCLK1
DI CDS Reference Level Sampling Clock
2
CDSCLK2
DI CDS Data Level Sampling Clock
3
ADCCLK
DI A/D Converter Sampling Clock
4
OEB
DI Output Enable, Active Low
5
DRVDD
P Digital Output Driver Supply
6
DRVSS
P Digital Output Driver Ground
7 D7 DO Data Output MSB. ADC DB13 High Byte, ADC DB5 Low Byte
8 D6 DO Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
9 D5 DO Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
10 D4 DO Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
11 D3 DO Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
12 D2 DO Data Output. ADC DB8 High Byte, ADC DB0 Low Byte
13 D1 DO Data Output. ADC DB7 High Byte, Don’t Care Low Byte
14 D0 DO Data Output LSB. ADC DB6 High Byte, Don’t Care Low Byte
15
SDATA
DI/DO
Serial Interface Data Input/Output
16
SCLK
DI Serial Interface Clock Input
17
SLOAD
DI Serial Interface Load Pulse
18 AVDD P +5 V Analog Supply
19 AVSS P Analog Ground
20
CAPB
AO ADC Bottom Reference Voltage Decoupling
21
CAPT
AO ADC Top Reference Voltage Decoupling
22 VINB AI Analog Input, Blue Channel
23
CML
AO Internal Bias Level Decoupling
24 VING AI Analog Input, Green Channel
25
OFFSET
AO Clamp Bias Level Decoupling
26
VINR
AI Analog Input, Red Channel
27 AVSS P Analog Ground
28 AVDD P +5 V Analog Supply
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
Figure 2 – Terminal Connections and Pin Function Descriptions
ASD0016515 Rev. D | Page 2 of 7
Free Datasheet http://www.datasheet4u.com/

No Preview Available !

4.0 Absolute Maximum Ratings. (TA = 25°C, unless otherwise noted)
AD9814S
Parameter
VIN, CAPT, CAPB
Digital Inputs
AVDD
DRVDD
AVSS
Digital Outputs
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
With respect to
AVSS
AVSS
AVSS
DRVSS
DRVSS
DRVSS
Min
-0.3
-0.3
-0.5
-0.5
-0.3
-0.3
-65
Max
AVDD + 0.3
AVDD + 0.3
+6.5
+6.5
+0.3
DRVDD + 0.3
+150
+150
+300
Units
V
V
V
V
V
V
°C
°C
°C
NOTES:
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional
operation of the device at these or other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect device reliability.
The input limits are defined as maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of
the device. Signals beyond the input limits will turn on the overvoltage protection diodes.
5.0 Thermal Characteristics:
Package Type
Thermal Resistance,
Bottom Brazed (F)
Junction-to-
Case
(ΘJC)
22
Junction-to-Ambient
(ΘJA)
60
Units
°C/W Max
ASD0016515 Rev. D | Page 3 of 7
Free Datasheet http://www.datasheet4u.com/

No Preview Available !

AD9814S
6.0 Table I. Electrical Table:
Parameter
See notes at end of table
RESOLUTION
Supply Currents
Power dissipation
Power supply rejection
ACCURACY (Entire Signal Path)
Integral Nonlinearity 2/
ACCURACY (Entire Signal Path)
Differential Nonlinearity
ACCURACY (Entire Signal Path)
Offset Error
ACCURACY (Entire Signal Path)
Gain Error 3/
PGA Gain Ratio 4/
Table I
Symbol
RES
Conditions 1/
Unless Otherwise Specified
No Missing Codes
Sub
Group
1,2,3
Limit Min
14
Limit Max
IAVDD
IDRVDD
PD
PSR AVDD= +5.0V ± 0.25V
INL
DNL
VOS
1,2,3
1,2,3
1,2,3
1,2
3
1,2
3
1
2
3
1,2,3
-11
-18
-1
-1
-1
-104
80
10
450
0.3
0.5
11
11
1.25
1
1.5
104
Units
Bits
mA
mA
mW
%FSR
%FSR
LSB
LSB
LSB
LSB
LSB
mV
GAIN
1,2,3
-5.3
5.3 %FSR
PGA GAIN
1,2,3
5.7
5.9
DIFFERENTIAL VREF
CAPT-CAPB (4V Input Range)
VREF4
1,2,3
1.9
2.1
V
DIFFERENTIAL VREF
CAPT-CAPB (2V Input Range)
VREF2
1,2,3
0.94
1.06
V
TABLE I NOTES:
1/ TA = +25 °C, TA Max = +125 °C, TA Min = -55 °C. AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS, FADCCLK = 6 MHz, FCDSCLK1 = FCDSCLK2 = 2
MHz, PGA Gain = 1, Input Range = 4V, unless otherwise noted.
2/ INL is measured using the “fixed endpoint” method, NOT using a “best-fit” calculation.
3/ The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.
4/ The PGA Gain is approximately “linear in dB” and follows the equation: PGA Gain = (5.8 / (1 + 4.8 (63 – G) / 63)) where G is the register
value.
ASD0016515 Rev. D | Page 4 of 7
Free Datasheet http://www.datasheet4u.com/

No Preview Available !

AD9814S
Figure 3 – 3-Channel CDS Mode Timing Diagram
Figure 4 – 3-Channel SHA Mode Timing Diagram
ASD0016515 Rev. D | Page 5 of 7
Free Datasheet http://www.datasheet4u.com/