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LTC2607/LTC2617/LTC2627
16-/14-/12-Bit Dual Rail-to-Rail
DACs with I2C Interface
Features
Description
n Smallest Pin-Compatible Dual DACs:
LTC2607: 16 Bits
LTC2617: 14 Bits
LTC2627: 12 Bits
n Guaranteed Monotonic Over Temperature
n 27 Selectable Addresses
n 400kHz I2C Interface
n Wide 2.7V to 5.5V Supply Range
n Low Power Operation: 260µA per DAC at 3V
n Power Down to 1µA, Max
n High Rail-to-Rail Output Drive (±15mA, Min)
n Ultralow Crosstalk (30µV)
n Double-Buffered Data Latches
n Asynchronous DAC Update Pin
n LTC2607/LTC2617/LTC2627: Power-On Reset to
Zero Scale
n LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset
to Mid-Scale
n Tiny (3mm × 4mm) 12-Lead DFN Package
Applications
n Mobile Communications
n Process Control and Industrial Automation
n Instrumentation
n Automatic Test Equipment
The LTC®2607/LTC2617/LTC2627 are dual 16-, 14- and
12-bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a
12-lead DFN package. They have built-in high performance
output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.
The parts use a 2-wire, I2C compatible serial interface. The
LTC2607/LTC2617/LTC2627 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.
The LTC2607/LTC2617/LTC2627 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2607-1/LTC2617-1/
LTC2627-1 to mid-scale. The voltage outputs stay at mid-
scale until a valid write and update takes place.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5396245 and 6891433. Patent Pending.
Block Diagram
REFLO 11
GND 10
12
VOUTA
12-/14-/16-BIT DAC
DAC REGISTER
REF 9
VCC 8
12-/14-/16-BIT DAC
7
VOUTB
DAC REGISTER
INPUT REGISTER
INPUT REGISTER
32-BIT SHIFT REGISTER
CA0 1 CA1 2 LDAC 3
2-WIRE INTERFACE
SCL 4
SDA 5
CA2 6
2607 BD01a
Differential Nonlinearity
(LTC2607)
1.0 VCC = 5V
0.8 VREF = 4.096V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0 0
16384
32768
CODE
49152 65535
2607 BD01b
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LTC2607/LTC2617/LTC2627
Absolute Maximum Ratings
(Note 1)
Any Pin to GND............................................. –0.3V to 6V
Any Pin to VCC.............................................. –6V to 0.3V
Maximum Junction Temperature........................... 125°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)................... 300°C
Operating Temperature Range:
LTC2607C/LTC2617C/LTC2627C
LTC2607C-1/LTC2617C-1/LTC2627C-1..... 0°C to 70°C
LTC2607I/LTC2617I/LTC2627I
LTC2607I-1/LTC2617I-1/LTC2627I-1....–40°C to 85°C
Pin Configuration
TOP VIEW
CA0
CA1
LDAC
SCL
SDA
CA2
1
2
3
4
5
6
12 VOUTA
11 REFLO
13 10 GND
9 REF
8 VCC
7 VOUTB
DE12 PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2607CDE#PBF
LTC2607CDE#TRPBF
2607
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2607IDE#PBF
LTC2607IDE#TRPBF
2607
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2607CDE-1#PBF
LTC2607CDE-1#TRPBF 26071
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2607IDE-1#PBF
LTC2607IDE-1#TRPBF 26071
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2617CDE#PBF
LTC2617CDE#TRPBF
2617
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2617IDE#PBF
LTC2617IDE#TRPBF
2617
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2617CDE-1#PBF
LTC2617CDE-1#TRPBF 26171
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2617IDE-1#PBF
LTC2617IDE-1#TRPBF 26171
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2627CDE#PBF
LTC2627CDE#TRPBF
2627
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2627IDE#PBF
LTC2627IDE#TRPBF
2627
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2627CDE-1#PBF
LTC2627CDE-1#TRPBF 26271
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LTC2627IDE-1#PBF
LTC2627IDE-1#TRPBF 26271
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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LTC2607/LTC2617/LTC2627
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications
VOUT unloaded, unless otherwise noted.
are
at
TA
=
25°C.
REF
=
4.096V
(VCC
=
5V),
REF
=
2.048V
(VCC
=
2.7V),
REFLO
=
0V,
LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution
l 12 14 16
Bits
Monotonicity
(Note 2)
l 12 14 16
Bits
DNL Differential Nonlinearity (Note 2)
l ±0.5
±1
±1 LSB
INL Integral Nonlinearity (Note 2)
l ±1.5 ±4
±5 ±16
±19 ±64
LSB
Load Regulation
ZSE Zero-Scale Error
V REIFO=UTV=CC0=m5AV,toM1id5-mSAcaSleourcing
IOUT = 0mA to 15mA Sinking
VREF = VCC = 2.7V, Mid-Scale
IOUT = 0mA to 7.5mA Sourcing
IOUT = 0mA to 7.5mA Sinking
Code = 0
l
l
l
l
l
0.02 0.125
0.03 0.125
0.04 0.25
0.05 0.25
19
0.1 0.5
0.1 0.5
0.2 1
0.2 1
19
0.35 2 LSB/mA
0.42 2 LSB/mA
0.7 4 LSB/mA
0.8 4 LSB/mA
19
mV
VOS Offset Error
CVoOSefTfiecmiepnet rature
(Note 6)
l ±1 ±9
±7
±1 ±9
±7
±1 ±9
±7
mV
µV/°C
GE Gain Error
l ±0.15 ±0.7 ±0.15 ±0.7 ±0.15 ±0.7 %FSR
Gain Temperature
Coefficient
±4 ±4 ±4 ppm/°C
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V, VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
PSR Power Supply Rejection
ROUT
DC Output Impedance
DC Crosstalk (Note 4)
VCC ±10%
VREF = VCC = 5V, Mid-Scale;
–15mA ≤ IOUT ≤ 15mA
VREF = VCC = 2.7V, Mid-Scale;
–7.5mA ≤ IOUT ≤ 7.5mA
Due to Full Scale Output Change (Note 5)
Due to Load Current Change
Due to Powering Down (Per Channel)
l
l
–80
0.032
0.035
±4
±3
±30
dB
0.15 Ω
0.15 Ω
µV
µV/mA
µV
ISC Short-Circuit Output Current
Reference Input
VCCC=o5d.e5:VZ,eVrRoESF c=a5le.;5FVorcing Output to VCC l
15
36
60 mA
Code: Full Scale; Forcing Output to GND l 15 37 60 mA
VCC = 2.7V, VREF = 2.7V
Code: Zero Scale; Forcing Output to VCC l 7.5 22 50 mA
Code: Full Scale; Forcing Output to GND l 7.5 30 50 mA
Input Voltage Range
Resistance
Normal Mode
l0
l 44
VCC V
64 80 kΩ
Capacitance
30 pF
IREF Reference Current, Power Down Mode
DAC Powered Down
l
0.001
1
µA
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LTC2607/LTC2617/LTC2627
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications
VOUT unloaded, unless otherwise noted.
are
at
TA
=
25°C.
REF
=
4.096V
(VCC
=
5V),
REF
=
2.048V
(VCC
=
2.7V),
REFLO
=
0V,
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Power Supply
VCC Positive Supply Voltage
ICC Supply Current
Digital I/O (Note 11)
For Specified Performance
l 2.7
5.5 V
VVCCCC
=
=
5V
3V
(Note
(Note
3)
3)
DAC Powered Down (Note 3) VCC = 5V
DAC Powered Down (Note 3) VCC = 3V
l
l
l
l
0.66 1.3 mA
0.52 1 mA
0.4 1 µA
0.10 1
µA
VIL
VIH
VIL(LDAC)
Low Level Input Voltage (SDA and SCL)
High Level Input Voltage (SDA and SCL)
Low Level Input Voltage (LDAC)
VIH(LDAC) High Level Input Voltage (LDAC)
VIL(CAn)
Low Level Input Voltage on CAn
(n = 0, 1, 2)
VVCCCC
=
=
4.5V
2.7V
to
to
5.5V
5.5V
VVCCCC
=
=
2.7V
2.7V
to
to
5.5V
3.6V
See Test Circuit 1
l
l 0.7VCC
l
l
l 2.4
l 2.0
l
0.3VCC
0.8
0.6
0.15VCC
V
V
V
V
V
V
V
VIH(CAn)
RINH
RINL
High Level Input Voltage on CAn (n = 0, 1, 2)
Resistance from CAn (n = 0, 1, 2)
to VCC to Set CAn = VCC
Resistance from CAn (n = 0, 1, 2)
to GND to Set CAn = GND
See Test Circuit 1
See Test Circuit 2
See Test Circuit 2
l 0.85VCC
l
l
V
10 kΩ
10 kΩ
RINF
Resistance from CAn (n = 0, 1, 2)
to VCC or GND to Set CAn = Float
See Test Circuit 2
VOL Low Level Output Voltage
Sink Current = 3mA
tOF Output Fall Time
VCOB
=
=
1V0IHp(FMtINo)4to00VpOF
=(NVoILte(M9A)X),
tSP Pulse Width of Spikes Suppressed by Input Filter
IIN Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
CIN I/O Pin Capacitance
Note 12
CB Capacitive Load for Each Bus Line
CCAX External Capacitive Load on Address
Pins CAn (n = 0, 1, 2)
l2
l0
l 20 + 0.1CB
l0
l
l
l
l
0.4 V
250 ns
50 ns
1 µA
10 pF
400 pF
10 pF

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LTC2607/LTC2617/LTC2627
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications
VOUT unloaded, unless otherwise noted.
are
at
TA
=
25°C.
REF
=
4.096V
(VCC
=
5V),
REF
=
2.048V
(VCC
=
2.7V),
REFLO
=
0V,
LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
tS Settling Time (Note 7)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
7
7 7 µs
9 9 µs
10 µs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits)
2.7
2.7
2.7 µs
(Note 8)
±0.006% (±1LSB at 14 Bits)
4.8 4.8 µs
±0.0015% (±1LSB at 16 Bits)
5.2 µs
Voltage Output Slew Rate
0.8 0.8 0.8 V/µs
Capacitive Load Driving
1000 1000 1000 pF
Glitch Impulse
At Mid-Scale Transition
12 12 12 nV • s
Multiplying Bandwidth
180 180 180 kHz
en Output Voltage Noise Density At f = 1kHz
At f = 10kHz
120 120 120 nV/√Hz
100 100 100 nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15 15 15 µVP-P
Timing Characteristics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VCC = 2.7V to 5.5V
fSCL SCL Clock Frequency
tHD(STA) Hold Time (Repeated) Start Condition
tLOW Low Period of the SCL Clock Pin
tHIGH High Period of the SCL Clock Pin
tSU(STA) Set-Up Time for a Repeated Start Condition
tHD(DAT) Data Hold Time
tSU(DAT) Data Set-Up Time
tr Rise Time of Both SDA and SCL Signals
tf Fall Time of Both SDA and SCL Signals
tSU(STO) Set-Up Time for Stop Condition
tBUF Bus Free Time Between a Stop and Start Condition
t1
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
(Note 9)
(Note 9)
l0
l 0.6
l 1.3
l 0.6
l 0.6
l0
l 100
l 20 + 0.1CB
l 20 + 0.1CB
l 0.6
l 1.3
l 400
400 kHz
µs
µs
µs
µs
0.9 µs
ns
300 ns
300 ns
µs
µs
ns
t2 LDAC Low Pulse Width
l 20
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note
2N –
2:
1,
wLihneeraerNityisanthdemreosnoolutotnioincitayndarkeLdiesfignievdenfrboymkLco=d0e.0k1L6to(2cNo/dVeREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL and LDAC at 0V or VCC, CA0, CA1 and CA2 Floating.
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with
the measured DAC at mid-scale, unless otherwise noted.
Note 5: RL = 2kΩ to GND or VCC.
Note 6: Inferred from measurement at code kL (Note 2) and at full scale.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specifications apply to LTC2607/LTC2607-1,
LTC2617/LTC2617-1, LTC2627/LTC2627-1.
Note 12: Guaranteed by design and not production tested.
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