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Integrated
Circuit
Systems, Inc.
ICS9250-08
Frequency Generator & Integrated Buffers for Celeron & PII/III
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
• 3 - CPUs @2.5V, up to 150MHz.
• 17 - SDRAM @ 3.3V, up to 150MHz.
• 7 - PCI @3.3V
• 2 - IOAPIC @ 2.5V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 150MHz frequency support
• Support power management: CPU, PCI, stop and Power
down Mode form I2C programming.
• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
• Uses external 14.318MHz crystal
Key Specifications:
• CPU – CPU: <175ps
• CPU – PCI: min = 1ns max = 4ns
• PCI – PCI: <250ps
• SDRAM - SDRAM: <500ps
Block Diagram
Pin Configuration
VDDREF
*FS2/REF1
*PCI_STOP/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
{I 2 C
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDLIOAPIC
55 IOAPIC0
54 IOAPIC_F
53 GND
52 CPUCLK_F
51 CPUCLK1
50 VDDLCPU
49 CPUCLK2
48 GND
47 CPU_STOP#
46 SDRAM_F
45 VDDSDR
44 SDRAM0
43 SDRAM1
42 GND
41 SDRAM2
40 SDRAM3
39 SDRAM4
38 SDRAM5
37 VDDSDR
36 SDRAM6
35 SDRAM7
34 GND
33 SDRAM12
32 SDRAM13
31 VDD48
30 24MHz/FS0*
29 48MHz/FS1*
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
PLL2
X1 XTAL
X2 OSC
÷2
STOP
FS[3:0]
MODE
CPU_STOP#
PCI_STOP#
{I 2 C
SCLK
SDATA
BUFFERIN
PLL1
Spread
Spectrum
LATCH
POR
4
Control
Logic
Config.
Reg.
STOP
PCI
CLOCK
DIVDER
STOP
STOP
48MHz
24MHz
IOAPIC_F
IOAPIC0
REF [1:0]
2
CPUCLK_F
1
CPUCLK [2:1]
2
6 PCICLK [5:0]
PCICLK_F
16 SDRAM [15:0]
SDRAM_F
Functionality
FS3 FS2 FS1 FS0
1111
1 1 10
110 1
1 10 0
10 11
10
10
100 1
10 0 0
0 111
0 110
0 10 1
0 100
00 11
00 10
000 1
0000
CPU
(MHz)
133
124
150
140
105
110
115
120
100.3
133
112
103
66.8
83.3
75
124
PCICLK (MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.67 (CPU/3)
38.33 (CPU/3)
40.00 (CPU/3)
33.43 (CPU/3)
44.33 (CPU/3)
37.33 (CPU/3)
34.33 (CPU/2)
33.40 (CPU/2)
41.65 (CPU/2)
37.5 (CPU/2)
41.33 (CPU/2)
9250-08 Rev H 10/8/99
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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ICS9250-08
Pin Configuration
PIN NUMBER
2
3
PIN NAME
REF1
FS21
REF0
PCI_STOP#1
4, 10, 23, 26, 34, 42,
48, 53
GND
5 X1
6 X2
PCICLK_F
8
MODE1
FS31
9
PCICLK0
TYPE
OUT
IN
OUT
IN
DESCRIPTION
14.318 MHz reference clock output
Latched frequency select input. Has pull-up to VDDPCI
14.318MHz reference clock output
Halts PCICLK [5:0] at logic "0" level when low.
(in mobile, MODE=0)
PWR Ground.
IN
OUT
OUT
IN
IN
OUT
14.318MHz input. Has internal load cap, (nominal 33pF).
Crystal output. Has internal load cap (33pF) and feedback
resistor to X1
Free running BUS clock not affected by PCI_STOP#
Latched input for MODE select. Converts pin 3 to PCI_STOP# when
low for power management.
Latched frequency select input, pull-down
Free running BUS clock not affected by PCI_STOP#
16, 14, 13, 12, 11 PCICLK [5:1]
OUT PCI Clock Outputs.
17
27
28
30
29
1, 7, 15, 20,
31, 37, 45
24, 25, 32, 33, 18,
19, 21, 22, 35, 36,
38, 39, 40, 41, 43,
44
BUFFERIN
SDATA
SCLK
24MHz
FS01
48MHz
FS11
VDDPCI, VDDREF,
VDDSDR, VDD48
SDRAM [15:0]
46 SDRAM_F
IN
IN
IN
OUT
IN
OUT
IN
PWR
Input for Buffers
Serial data in for serial config port. (I2C)
Clock input for serial config port. (I2C)
24MHz clock output for Super I/O or FD.
Latched frequency select input. Has pull-up to VDD4.
48MHz clock output for USB.
Latched frequency select input. Has pull-up to VDD2.
Nominal 3.3V power supply, see power groups for function.
OUT SDRAM clocks
OUT Free running SDRAM clock Not affected by CPU_STOP#
47
50, 56
55
51, 49
52
54
CPU_STOP#
VDDLCPU,
VDDLIOAPIC
IOAPIC0
CPUCLK [2:1]
CPUCLK_F
IOAPIC_F
IN
PWR
OUT
OUT
OUT
OUT
Halts CPUCLK [2:1], IOAPIC0, SDRAM [15:0]
clocks at logic "0" level when low.
CPU and IOAPIC clock buffer power supply, 2.5V nominal.
IOAPIC clock output. (14.318 MHz) Poweredby VDDLIOAPIC
CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
Free running CPU output clock. Not affected ty the CPU_STOP#.
Freerunning IOAPIC clock output. Not affected by the CPU_STOP#
(14.31818 MHz) Powered by VDDLIOAPIC
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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General Description
The ICS9250-08 is the single chip clock solution for Desktop/
designs using BX, Appollo Pro 133 type of chip sets. It provides
all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9250-08
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE
(Latched Input)
0
1
PCI_STOP#
(Input)
REF0
(Output)
ICS9250-08
Power Groups
VDDREF = REF [1:0], X1, X2
VDDPCI = PCICLK_F, PCICLK [5:0]
VDDSDR = SDRAM [15:0], supply for PLL core,
VDD48 = 48MHz, 24MHz
VDDLIOAPIC = IOAPIC_F
VDDLCPU = CPUCLK_F [2:1]
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ICS9250-08
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
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Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit 2,
Bit 6:4
Bit 3
Bit 1
Bit 0
Description
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit2 Bit6 Bit5 Bit4 CPU clock
PCI
0111
0110
100.3
133
33.43 (CPU/3)
44.33 (CPU/3)
0101
0100
112 37.33 (CPU/3)
103 34.3 (CPU/3)
0011
0010
66.8 33.4 (CPU/2)
83.3 41.65(CPU/2)
0001
0000
75 37.5 (CPU/2)
124 41.33 (CPU/3)
1111
1110
133 33.25 (CPU/4)
124 31.00 (CPU/4)
1101
1100
150 37.50 (CPU/4)
140 35.00 (CPU/4)
1011
1010
105 35.00 (CPU/3)
110 36.67 (CPU/3)
1001
1000
115 38.33 (CPU/3)
120 40.00 (CPU/3)
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 6:4 (above)
0 - Normal
1 - Spread Spectrum Enabled (Center Spread)
0 - Running
1- Tristate all outputs
PWD
0
Note1
0
0
0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 2, 4, 5,
6 are default to 0000, and if bit 3 is written to a 1 to use Bits 2, 6:4, then these
should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
ICS9250-08
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5
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