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UPI-41AH 42AH
UNIVERSAL PERIPHERAL INTERFACE
8-BIT SLAVE MICROCONTROLLER
Y UPI-41 6 MHz UPI-42 12 5 MHz
Y Pin Software and Architecturally
Compatible with all UPI-41 and UPI-42
Products
Y 8-Bit CPU plus ROM OTP EPROM RAM
I O Timer Counter and Clock in a
Single Package
Y 2048 x 8 ROM OTP 256 x 8 RAM on
UPI-42 1024 x 8 ROM OTP 128 x 8
RAM on UPI-41 8-Bit Timer Counter 18
Programmable I O Pins
Y One 8-Bit Status and Two Data
Registers for Asynchronous Slave-to-
Master Interface
Y DMA Interrupt or Polled Operation
Supported
Y Fully Compatible with all Intel and Most
Other Microprocessor Families
Y Interchangeable ROM and OTP EPROM
Versions
Y Expandable I O
Y Sync Mode Available
Y Over 90 Instructions 70% Single Byte
Y Available in EXPRESS
Standard Temperature Range
Y inteligent Programming Algorithm
Fast OTP Programming
Y Available in 40-Lead Plastic and 44-
Lead Plastic Leaded Chip Carrier
Packages
(See Packaging Spec Order 240800-001)
Package Type P and N
The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer
to develop customized solutions for peripheral device control
They are essentially ‘‘slave’’ microcontrollers or microcontrollers with a slave interface included on the chip
Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS
Modules and iAPX family as well as other 8- 16- and 32-bit systems
To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM
(OTP) All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to
production level designs
210393 – 2
Figure 1 DIP Pin Configuration
November 1994
210393 – 3
Figure 2 PLCC Pin Configuration
Order Number 210393-008
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UPI-41AH 42AH
Figure 3 Block Diagram
210393 – 1
UPI PRODUCT MATRIX
UPI
Device
ROM
8042AH
2K
8242AH
2K
8742AH
8041AH
1K
8741AH
OTP
EPROM
2K
1K
RAM
256
256
256
128
128
Programming
Voltage
12 5V
12 5V
THE INTEL 8242
As shown in the UPI-42 product matrix the UPI-42
will be offered as a pre-programmed 8042 with sev-
eral software vendors’ keyboard controller firmware
The current list of available 8242 versions include
keyboard controller firmware from both Phoenix
Technologies Ltd IBM and Award Software Inc
The 8242 is programmed with Phoenix Technologies
Ltd keyboard controller firmware for AT-compatible
systems This keyboard controller is fully compatible
with all AT-compatible operating systems and appli-
cations The 8242PC also contains Phoenix Tech-
nologies Ltd firmware This keyboard controller
provides support for AT PS 2 and most EISA plat-
forms as well as PS 2-style mouse support for either
AT or PS 2 platforms
The Intel 8242BB is programmed with IBM’s key-
board controller firmware The 8242BB provides an
off the shelf keyboard and auxiliary device controller
for AT PS 2 EISA and PCI architectures
The 8242WA contains Award Software Inc firm-
ware This device provides at AT-compatible key-
board controller for use in IBM PC AT compatible
computers The 8242WB contains a version of
Award Software Inc firmware that provides PS 2
style mouse support in addition to the standard fea-
tures of the 8242WA
Contact factory for current code revision available in all versions of the 8242 product lines
2
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UPI-41AH 42AH
Table 1 Pin Description
DIP PLCC
Symbol Pin Pin Type
No No
Name and Function
TEST 0 1 2 I TEST INPUTS Input pins which can be directly tested using conditional branch
TEST 1 39 43
instructions
FREQUENCY REFERENCE TEST 1 (T1) also functions as the event timer input (under
software control) TEST 0 (T0) is used during PROM programming and ROM EPROM
verification It is also used during Sync Mode to reset the instruction state to S1 and
synchronize the internal clock to PH1 See the Sync Mode Section
XTAL 1 2 3 I INPUTS Inputs for a crystal LC or an external timing signal to determine the internal
XTAL 2 3
4
oscillator frequency
RESET 4 5 I RESET Input used to reset status flip-flops and to set the program counter to zero
RESET is also used during EPROM programming and verification
SS 5 6 I SINGLE STEP Single step input used in conjunction with the SYNC output to step the
program through each instruction (EPROM) This should be tied to a5V when not used
This pin is also used to put the device in Sync Mode by applying 12 5V to it
CS 6 7 I CHIP SELECT Chip select input used to select one UPI microcomputer out of several
connected to a common data bus
EA 7 8 I EXTERNAL ACCESS External access input which allows emulation testing and
ROM EPROM verification This pin should be tied low if unused
RD 8 9 I READ I O read input which enables the master CPU to read data and status words from
the OUTPUT DATA BUS BUFFER or status register
A0 9 10 I COMMAND DATA SELECT Address Input used by the master processor to indicate
whether byte transfer is data (A0 e 0 F1 is reset) or command (A0 e 1 F1 is set) A0 e 0
during program and verify operations
WR 10 11 I WRITE I O write input which enables the master CPU to write data and command words
to the UPI INPUT DATA BUS BUFFER
SYNC
11 13 O OUTPUT CLOCK Output signal which occurs once per UPI instruction cycle SYNC can
be used as a strobe for external circuitry it is also used to synchronize single step
operation
D0 – D7 12 – 19 14 – 21 I O DATA BUS Three-state bidirectional DATA BUS BUFFER lines used to interface the UPI
(BUS)
microcomputer to an 8-bit master system data bus
P10 – P17 27 – 34 30 – 33 I O PORT 1 8-bit PORT 1 quasi-bidirectional I O lines P10 – P17 access the signature row
35– 38
and security bit
P20 – P27 21 – 24 24 – 27 I O PORT 2 8-bit PORT 2 quasi-bidirectional I O lines The lower 4 bits (P20 – P23) interface
35 – 38 39– 42
directly to the 8243 I O expander device and contain address and data information during
PORT 4 – 7 access The upper 4 bits (P24 – P27) can be programmed to provide interrupt
Request and DMA Handshake capability Software control can configure P24 as Output
Buffer Full (OBF) interrupt P25 as Input Buffer Full (IBF) interrupt P26 as DMA Request
(DRQ) and P27 as DMA ACKnowledge (DACK)
PROG 25 28 I O PROGRAM Multifunction pin used as the program pulse input during PROM programming
During I O expander access the PROG pin acts as an address data strobe to the 8243
This pin should be tied high if unused
VCC
VDD
40 44
26 29
POWER a5V main power supply pin
POWER a5V during normal operation a12 5V during programming operation Low
power standby supply pin
VSS 20 22
GROUND Circuit ground potential
3
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