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PRELIMINARY
8XC251SA/SB/SP/SQ
HIGH-PERFORMANCE
CHMOS MICROCONTROLLER
Commercial/Express
s Real-time and Programmed Wait State
Bus Operation
s Binary-code Compatible with MCS® 51
s Pin Compatible with 44-pin PLCC and 40-
pin PDIP MCS 51 Sockets
s Register-based MCS® 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes, Words,
or Double Words
s Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and Logic
Instructions
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
s Linear Addressing
s 256-Kbyte Expanded External Code/Data
Memory Space
s ROM/OTPROM/EPROM Options:
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
without ROM/OTPROM/EPROM
s 16-bit Internal Code Fetch
s 64-Kbyte Extended Stack Space
s On-chip Data RAM Options:
1-Kbyte (SA/SB) or 512-Byte (SP/SQ)
s 8-bit, 2-clock External Code Fetch in
Page Mode
s Fast MCS 251 Instruction Pipeline
s User-selectable Configurations:
— External Wait States (0-3 wait states)
— Address Range & Memory Mapping
— Page Mode
s 32 Programmable I/O Lines
s Seven Maskable Interrupt Sources
with Four Programmable Priority
Levels
s Three Flexible 16-bit Timer/counters
s Hardware Watchdog Timer
s Programmable Counter Array
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
s Programmable Serial I/O Port
— Framing Error Detection
— Automatic Address Recognition
s High-performance CHMOS Technology
s Static Standby to 16-MHz Operation
s Complete System Development
Support
— Compatible with Existing Tools
— New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
s Package Options (PDIP, PLCC, and
Ceramic DIP)
A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code
compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51
microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and
efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.
A variety of features can be selected by new user-programmable configurations.
COPYRIGHT © INTEL CORPORATION, 1996
May 1996
Order Number: 272783-003
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8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
System Bus and I/O Ports
P0.7:0
P2.7:0
Port 0
Drivers
Port 2
Drivers
Code
OTPROM/ROM
8 Kbytes
or
16 Kbytes
Data RAM
512 Bytes
or
1024 Bytes
I/O Ports and
Peripheral Signals
P1.7:0
P3.7:0
Port 1
Drivers
Port 3
Drivers
Memory Data (16)
Memory Address (16)
Bus Interface
Code Bus (16)
Code Address (24)
Instruction Sequencer
SRC1 (8)
Peripheral
Interface
Interrupt
Handler
Watchdog
Timer
Timer/
Counters
PCA
SRC2 (8)
ALU
Register
File
Data
Memory
Interface
Clock
&
Reset
Serial I/O
Peripherals
DST (16)
MCS® 251 Microcontroller Core
Clock & Reset
8XC251SA/SB/SP/SQ Microcontroller
Figure 1. 8XC251SA/SB/SP/SQ Block Diagram
PRELIMINARY
A4214-01
3
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