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STF13NK50Z
STP13NK50Z, STW13NK50Z
N-channel 500 V, 0.40 , 11 A TO-220, TO-220FP, TO-247
Zener-protected SuperMESHTM Power MOSFET
Features
Type
STF13NK50Z
STP13NK50Z
STW13NK50Z
VDSS
RDS(on)
max
ID
Pw
500 V
500 V
500 V
<0.48 11 A
<0.48 11 A
<0.48 11 A
30 W
140 W
140 W
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitances
Very good manufacturing repeatability
Applications
Switching application
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs.
3
2
1
TO-220
3
2
1
TO-220FP
3
2
1
TO-247
Figure 1. Internal schematic diagram
Table 1. Device summary
Order code
STF13NK50Z
STP13NK50Z
STW13NK50Z
Marking
F13NK50Z
P13NK50Z
W13NK50Z
Package
TO-220FP
TO-220
TO-247
March 2009
Rev 2
Packaging
Tube
Tube
Tube
1/15
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Contents
Contents
STx13NK50Z
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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STx13NK50Z
1 Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
TO-220, TO-247 TO-220FP
Unit
VDS
VGS
ID
ID
IDM(2)
PTOT
dv/dt(3)
Drain-source voltage (VGS = 0)
Gate-source voltage
Drain current (continuous)
at TC = 25 °C
Drain current (continuous)
at TC=100 °C
Drain current (pulsed)
Total dissipation at TC = 25 °C
Derating factor
Peak diode recovery voltage slope
500
± 30
11
11(1)
6.93
44
140
1.12
4.5
6.93(1)
44(1)
30
0.24
V
V
A
A
A
W
W/°C
V/ns
VISO
Insulation withstand voltage (RMS)
from all three leads to external heat sin
(t=1 s;TC= 25 °C)
TJ Operating junction temperature
Tstg Storage temperature
1. Limited only by maximum temperature allowed
2. Pulse width limited by safe operating area
3. ISD 11 A, di/dt 200 A/µs, VDD 80% V(BR)DSS
2500
-55 to 150
V
°C
Table 3. Thermal data
Symbol
Parameter
TO-220
Value
TO-247
Unit
TO-220FP
Rthj-case
Rthj-a
Tl
Thermal resistance junction-case max
Thermal resistance junction-ambient
max
Maximum lead temperature for
soldering purpose
0.89
62.5 50
300
4.17 °C/W
62.5 °C/W
°C
Table 4. Avalanche characteristics
Symbol
Parameter
Value
Unit
Avalanche current, repetitive or not-repetitive
IAR (pulse width limited by Tj Max)
Single pulse avalanche energy
EAS (starting TJ = 25 °C, ID = IAR, VDD= 50 V)
11 A
240 mJ
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Electrical characteristics
2 Electrical characteristics
STx13NK50Z
(TCASE = 25 °C unless otherwise specified)
Table 5.
Symbol
On/off states
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
IDSS
Zero gate voltage drain
current (VGS = 0)
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VDS = 0)
Gate threshold voltage
Static drain-source on
resistance
ID = 1 mA, VGS= 0
VDS = Max rating,
VDS = Max rating,
TC =125 °C
VGS = ± 20 V
VDS= VGS, ID = 100 µA
VGS= 10 V, ID= 6.5 A
Min. Typ. Max. Unit
500 V
1 µA
50 µA
±10 µA
3 3.75 4.5 V
0.4 0.48
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1)
Ciss
Coss
Crss
Forward transconductance
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =15 V, ID = 6.5 A
VDS =25 V, f=1 MHz,
VGS=0
8.5
1600
200
45
S
pF
pF
pF
Coss
(2)
eq .
Equivalent output
capacitance
VGS=0, VDS =0 V to 400 V
50
pF
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD=400 V, ID = 13 A
VGS =10 V
Figure 20
47 nC
9 nC
28 nC
Rg Intrinsic gate resistance
f= 1 MHz open drain
2.3
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Table 7.
Symbol
Switching times
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
VDD=400 V, ID=6.5 A,
RG=4.7 Ω, VGS=10 V
Figure 19
Min. Typ. Max. Unit
18 ns
23 ns
61 ns
24 ns
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STx13NK50Z
Electrical characteristics
Table 8.
Symbol
Source drain diode
Parameter
Test conditions
ISD
ISDM(1)
VSD(2)
Source-drain current
Source-drain current (pulsed)
Forward on voltage
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD=11 A, VGS=0
ISD=6.5 A,
di/dt = 100 A/µs,
VDD=40 V, Tj=25 °C
Figure 21
ISD=6.5 A,
di/dt = 100 A/µs,
VDD=40 V, Tj=150 °C
Figure 21
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Min Typ. Max Unit
11 A
44 A
1.6 V
380 ns
3.4 µC
18 A
425 ns
3.9 µC
18.5 A
Table 9.
Symbol
Gate-source Zener diode
Parameter
Test conditions
Min. Typ. Max. Unit
BVGSO (1)
Gate-source breakdown voltage
Igs=±1 mA
(open drain)
30
V
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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