2032VL.pdf 데이터시트 (총 12 페이지) - 파일 다운로드 2032VL 데이타시트 다운로드

No Preview Available !

ispLSI® 2032VL
2.5V In-System Programmable
SuperFAST™ High Density PLD
Features
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2032V and 2032VE Devices
• 2.5V LOW VOLTAGE 2032 ARCHITECTURE
— Interfaces With Standard 3.3V Devices (Inputs and
I/Os are 3.3V Tolerant)
— 45 mA Typical Active Current
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 180 MHz Maximum Operating Frequency
tpd = 5.0 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
A0
Global Routing Pool
(GRP)
A1
A2 GLB
A3
DQ
Logic D Q
Array D Q
DQ
A7
A6
A5
A4
Description
0139Bisp/2000
The ispLSI 2032VL is a High Density Programmable
Logic Device containing 32 Registers, 32 Universal I/O
pins, two Dedicated Input Pins, three Dedicated Clock
Input Pins, one dedicated Global OE input pin and a
Global Routing Pool (GRP). The GRP provides complete
interconnectivity between all of these elements. The
ispLSI 2032VL features in-system programmability
through the Boundary Scan Test Access Port (TAP) and
is 100% IEEE 1149.1 Boundary Scan Testable. The
ispLSI 2032VL offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 2032VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2032vl_02
1

No Preview Available !

Specifications ispLSI 2032VL
Functional Block Diagram
Figure 1. ispLSI 2032VL Functional Block Diagram
GOE 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TDO/IN 1
TMS/NC
BSCAN
A0
A1 Global Routing Pool
(GRP)
A2
A7
A6
A5
A3 A4
Generic Logic
Blocks (GLBs)
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
Note: *Y1 and RESET are multiplexed on the same pin
Y0
Y1*
TCK/Y2
0139B/2032VL
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control, and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 3.3 Volt signal levels
to support mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORPs. Each
ispLSI 2032VL device contains one Megablock.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2032VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
2

No Preview Available !

Specifications ispLSI 2032VL
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................ -0.5 to +4.05V
Input Voltage Applied ............................. -0.5 to +4.05V
Off-State Output Voltage Applied .......... -0.5 to +4.05V
Storage Temperature .............................. -65 to +150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
VCC
VIL
VIH
Supply Voltage
Input Low Voltage
Input High Voltage
PARAMETER
Commercial TA = 0°C to + 70°C
Industrial
TA = -40°C to + 85°C
Capacitance (TA=25°C, f=1.0 MHz)
MIN.
2.3
2.3
-0.3
1.7
MAX. UNITS
2.7 V
2.7 V
0.7 V
3.6 V
Table 2-0005/2032VL
SYMBOL
C1
C2
C3
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock Capacitance
TYPICAL
8
6
10
UNITS
pf
pf
pf
TEST CONDITIONS
VCC = 2.5V, VIN = 0.0V
VCC = 2.5V, VI/O = 0.0V
VCC = 2.5V, VY = 0.0V
Table 2-0006/2032VL
Erase Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
UNITS
Cycles
Table 2-0008A/2032VL
3

No Preview Available !

Specifications ispLSI 2032VL
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
3-state levels are measured 0.15V from
steady-state active level.
GND to VCC
1.5 ns
Figure 2. Test Load
VCC
VCC /2
VCC /2
See Figure 2
Table 2-0003/2032VL
Device
Output
R1
R2
Test
Point
CL*
Output Load Conditions (see Figure 2)
TEST CONDITION
A
Active High
B
Active Low
Active High to Z
C at VOH -0.15V
Active Low to Z
at VOL+0.15V
R1
250
250
R2
218
218
218
CL
35pF
35pF
35pF
5pF
250
5pF
Table 2-0004A/2032VL
*CL includes Test Fixture and Probe Capacitance.
0213A/2032VL
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VOL
Output Low Voltage
IOL = 100µA
IOL = 8mA
— — 0.2 V
— — 0.4 V
IOH = -100µA
VCC - 0.2 — — V
VOH
Output High Voltage
IOH = -1mA
2.0 — — V
IOH = -4mA
1.8 — — V
IIL5 Input or I/O Low Leakage Current
0V VIN VIL (Max.)
— — -10 µA
IIH Input or I/O High Leakage Current
VIH (min) VIN 3.6V
— — 10 µA
IIL-isp BSCAN Input Pull-Up Current
0V VIN VIL
— — -150 µA
IIL-PU I/O Active Pull-Up Current
0V VIN VIL
— — -150 µA
IOS1
ICC2, 4
Output Short Circuit Current
Operating Power Supply Current
VCC= 2.5V, VOUT= 0.5V
VIL = 0.0V, VIH = 2.5V
— — -100 mA
45
mA
fCLK = 1 MHz
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
Table 2-0007/2032VL
2. Measured using two 16-bit counters.
3. Typical values are at VCC = 2.5V and TA = 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC.
5. With no pull-up resistors.
4

No Preview Available !

Specifications ispLSI 2032VL
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 3
COND.
#
DESCRIPTION1
-180
-135
-110
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass 5.0 7.5 10.0 ns
tpd2
A 2 Data Propagation Delay
7.5 10.0 13.0 ns
fmax
A 3 Clock Frequency with Internal Feedback 2
180 135 110 MHz
fmax (Ext.)
fmax (Tog.)
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
)tco1
118
100
80.0
MHz
5 Clock Frequency, Max. Toggle
200 167 125 MHz
tsu1
6 GLB Reg. Setup Time before Clock, 4 PT Bypass 3.0 4.0 5.5 ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
4.0 4.5 5.0 ns
th1
8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 0.0 0.0 ns
tsu2
9 GLB Reg. Setup Time before Clock
4.5 5.5 7.5 ns
tco2
A 10 GLB Reg. Clock to Output Delay
5.0 5.5 6.0 ns
th2 11 GLB Reg. Hold Time after Clock
0.0 0.0 0.0 ns
tr1
A 12 Ext. Reset Pin to Output Delay, ORP Bypass
6.0 8.0 12.5 ns
trw1
13 Ext. Reset Pulse Duration
4.0 5.0 6.5 ns
tptoeen
B 14 Input to Output Enable
10.0 12.0 14.5 ns
tptoedis
C 15 Input to Output Disable
10.0 12.0 14.5 ns
tgoeen
B 16 Global OE Output Enable
5.0 6.0 7.0 ns
tgoedis
C 17 Global OE Output Disable
5.0 6.0 7.0 ns
twh 18 External Synchronous Clock Pulse Duration, High 2.5 3.0 4.0 ns
twl 19 External Synchronous Clock Pulse Duration, Low 2.5 3.0 4.0 ns
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2032VL
5