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ispLSI® 2096VE
3.3V In-System Programmable
SuperFAST™ High Density PLD
Features
Functional Block Diagram
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2096V Devices
— Pinout Compatible with ispLSI 2192VE
• 3.3V LOW VOLTAGE 2096 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
Output Routing Pool (ORP)
C7 C6 C5 C4
A0
DQ
A1 Logic D Q
A2 GLB Array D Q
DQ
A3
A4 A5 A6 A7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C3 C2 C1 C0
B7
Global Routing Pool
(GRP)
B6
B5
B4
B0 B1 B2 B3
Output Routing Pool (ORP)
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 250MHz* Maximum Operating Frequency
tpd = 4.0ns* Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
Description
0919/2096VE
The ispLSI 2096VE is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VE
features in-system programmability through the Bound-
ary Scan Test Access Port (TAP) and is 100% IEEE
1149.1 Boundary Scan Testable. The ispLSI 2096VE
offers non-volatile reprogrammability of the logic, as well
as the interconnect to provide truly reconfigurable sys-
tems.
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
The basic unit of logic on the ispLSI 2096VE device is the
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
*Advanced Information
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2096ve_05
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Specifications ispLSI 2096VE
Functional Block Diagram
Figure 1. ispLSI 2096VE Functional Block Diagram
Megablock
Generic Logic
Blocks (GLBs)
Input Bus
Output Routing Pool (ORP)
C7 C6 C5 C4
Input Bus
Output Routing Pool (ORP)
C3 C2 C1 C0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
RESET
BSCAN
A0
Global
A1 Routing
Pool
(GRP)
A2
A3
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
B0 B1 B2 B3
Output Routing Pool (ORP)
Input Bus
I/O 63
B7 I/O 62
I/O 61
I/O 60
I/O 59
B6 I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
B5 I/O 53
I/O 52
I/O 51
I/O 50
B4 I/O 49
I/O 48
0917/2096VE
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 5V signal levels to
support mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096VE device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Clocks in the ispLSI 2096VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
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Specifications ispLSI 2096VE
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.4V
Input Voltage Applied ............................... -0.5 to +5.6V
Off-State Output Voltage Applied ............ -0.5 to +5.6V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
VCC
VIL
VIH
Supply Voltage
Input Low Voltage
Input High Voltage
PARAMETER
Commercial TA = 0°C to + 70°C
Industrial
TA = -40°C to + 85°C
MIN.
3.0
3.0
VSS 0.5
2.0
MAX. UNITS
3.6 V
3.6 V
0.8 V
5.25 V
Table 2-0005/2096VE
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
C1
C2
C3
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock and Global Output Enable Capacitance
TYPICAL
8
6
10
UNITS
pf
pf
pf
TEST CONDITIONS
VCC = 3.3V, VIN = 0.0V
VCC = 3.3V, VI/O = 0.0V
VCC = 3.3V, VY = 0.0V
Table 2-0006/2096VE
Erase Reprogram Specifications
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10000
MAXIMUM
UNITS
Cycles
Table 2-0008/2096VE
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Specifications ispLSI 2096VE
Switching Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Time
1.5ns 10% to 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
Table 2-0003/2096VE
Output Load Conditions (see Figure 2)
Figure 2. Test Load
+ 3.3V
Device
Output
R1
R2
Test
Point
CL*
TEST CONDITION
A
Active High
B
Active Low
Active High to Z
C at VOH -0.5V
Active Low to Z
at VOL+0.5V
R1
316
316
R2
348
348
348
348
CL
35pF
35pF
35pF
5pF
*CL includes Test Fixture and Probe Capacitance.
0213A/2096VE
316
3485pF
Table 2-0004/2096VE
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN. TYP.3 MAX. UNITS
VOL
Output Low Voltage
IOL= 8 mA
– – 0.4 V
VOH
IIL
IIH
IIL-isp
IIL-PU
IOS1
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
BSCAN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
IOH = -4 mA
0V VIN VIL (Max.)
(VCC 0.2)V VIN VCC
VCC VIN 5.25V
0V VIN VIL
0V VIN VIL
VCC= 3.3V, VOUT = 0.5V
2.4 – – V
– – -10 µA
– – 10 µA
– – 10 µA
– – -150 µA
– – -150 µA
– – -100 mA
ICC2, 4 Operating Power Supply Current
VIL= 0.0V, VIH = 3.0V
fCLOCK = 1 MHz
125 mA
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
Table 2-0007A/2096VE
2. Measured using six 16-bit counters.
3. Typical values are at VCC= 3.3V and TA= 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
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Specifications ispLSI 2096VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 3
COND.
#
DESCRIPTION1
-250
-200
UNITS
MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass
4.0 4.5 ns
tpd2
A 2 Data Propagation Delay
— — — 7.0 ns
fmax
A 3 Clock Frequency with Internal Feedback 2
250 200 MHz
fmax (Ext.)
fmax (Tog.)
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
)tco1
5 Clock Frequency, Max. Toggle
— — 133 MHz
— — 200 MHz
tsu1
6 GLB Reg. Setup Time before Clock, 4 PT Bypass
— — 3.0 ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
— — — 3.5 ns
th1 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
— — 0.0 ns
tsu2
9 GLB Reg. Setup Time before Clock
— — 4.0 ns
tco2
A 10 GLB Reg. Clock to Output Delay
— — — 4.5 ns
th2 11 GLB Reg. Hold Time after Clock
— — 0.0 ns
tr1 A 12 Ext. Reset Pin to Output Delay
— — — 6.0 ns
trw1
13 Ext. Reset Pulse Duration
— — 4.0 ns
tptoeen
B 14 Input to Output Enable
— — — 8.0 ns
tptoedis
C 15 Input to Output Disable
— — — 8.0 ns
tgoeen
B 16 Global OE Output Enable
— — — 5.0 ns
tgoedis
C 17 Global OE Output Disable
— — — 5.0 ns
twh 18 External Synchronous Clock Pulse Duration, High
— — 2.5 ns
twl 19 External Synchronous Clock Pulse Duration, Low
— — 2.5 ns
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2096VE
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